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Model Perspective

May 29, 2026 · Industry Insights

Decoding Huawei’s τ (Tau) Law: Why Time‑Scaling May Replace Moore’s Geometry

The article examines Huawei’s newly announced τ (Tau) Law, which proposes scaling semiconductor performance by reducing signal‑propagation delay rather than shrinking transistor geometry, explains its RC‑delay model, logical‑folding technique, multi‑layer optimization framework, and compares it with existing 3D‑stacking approaches, while assessing its practical challenges and industry implications.

RC delaySTCOchip design

0 likes · 11 min read

Decoding Huawei’s τ (Tau) Law: Why Time‑Scaling May Replace Moore’s Geometry

Java Tech Enthusiast

May 29, 2026 · Industry Insights

What Is Huawei’s New “τ (Tau) Law” and How Does It Challenge Moore’s Law?

Huawei introduced the “τ (Tau) Law” at ISCAS 2026, proposing a shift from geometric scaling to time‑constant reduction to overcome the physical limits of Moore’s Law, and outlines how signal‑propagation delay can be compressed through system‑level innovations such as logical folding and advanced packaging.

HuaweiMoore's LawSignal Propagation

0 likes · 8 min read

What Is Huawei’s New “τ (Tau) Law” and How Does It Challenge Moore’s Law?

May 26, 2026 · Industry Insights

How Huawei’s “τ Law” Redefines Chip Scaling by Shrinking Time, Not Geometry

At ISCAS 2026, Huawei’s He Tingbo unveiled the “τ Law,” a time‑scaling theory that replaces geometric miniaturization with LogicFolding to cut signal‑travel time, delivering up to 55% higher transistor density, 41% better SoC efficiency, and a portfolio of 381 chips over six years.

HuaweiISCAS2026chip design

0 likes · 9 min read

How Huawei’s “τ Law” Redefines Chip Scaling by Shrinking Time, Not Geometry

IT Services Circle

May 26, 2026 · Industry Insights

What Is Huawei’s New “τ (Tau) Law” for Semiconductors?

Huawei introduced the “τ (Tau) Law” at the 2026 ISC conference, proposing a shift from geometric scaling of Moore’s law to “time miniaturization” that reduces signal propagation delay through logical folding and interconnect redesign, aiming to sustain semiconductor performance as transistor sizes near physical limits.

HuaweiMoore's Lawchip design

0 likes · 8 min read

What Is Huawei’s New “τ (Tau) Law” for Semiconductors?

Architects' Tech Alliance

May 25, 2026 · Industry Insights

Huawei’s τ (Tao) Scaling Theory: How Time‑Based Chip Design Breaks Performance Limits

Huawei’s new τ (Tao) scaling theory shifts chip optimisation from shrinking dimensions to compressing time, offering a post‑Moore roadmap that boosts mobile SoC density by 55%, AI data‑center latency by 500×, and promises continued performance growth without relying on advanced EUV lithography.

AI data centerHuaweiLogicFolding

0 likes · 8 min read

Huawei’s τ (Tao) Scaling Theory: How Time‑Based Chip Design Breaks Performance Limits

AI Large-Model Wave and Transformation Guide

May 25, 2026 · Industry Insights

When Moore’s Law Hits the Wall, China Takes a New Chip Road with Huawei’s “Tau Law”

Huawei’s He Tingbo announced at ISCAS 2026 that Moore’s geometric scaling has reached a physical ceiling and introduced the “Tau Law,” a time‑scaling strategy that leverages multi‑layer optimization, logic folding, and the Lingqu bus to achieve 1.4 nm‑equivalent performance without EUV, outlining a roadmap to 2026 and 2031.

EUVHuaweiMoore's Law

0 likes · 7 min read

When Moore’s Law Hits the Wall, China Takes a New Chip Road with Huawei’s “Tau Law”

Architects' Tech Alliance

May 25, 2026 · Industry Insights

What Is the ‘τ Law’? How Huawei Aims to Reach 1.4 nm‑Level Performance in Five Years

The article introduces Huawei’s “τ Law”, which shifts chip advancement from geometric scaling to time‑constant reduction, explains its four‑layer optimization (device, circuit, chip, system), showcases logic‑folding technology, and outlines a roadmap that could match 1.4 nm performance by 2031 without relying on EUV lithography.

HuaweiMoore's LawSystem Optimization

0 likes · 9 min read

What Is the ‘τ Law’? How Huawei Aims to Reach 1.4 nm‑Level Performance in Five Years

Architects' Tech Alliance

Apr 28, 2026 · Industry Insights

SpaceX’s Billion‑Dollar Gamble: The Ambitious Quest to Build Its Own Space‑Ready GPU

SpaceX is planning a multibillion‑dollar effort to design and manufacture a custom AI GPU that can survive the extreme temperature, radiation, and power constraints of space while also serving Tesla’s edge‑computing needs, confronting severe technical, ecosystem, and capital challenges.

AIGPUSpace Computing

0 likes · 9 min read

SpaceX’s Billion‑Dollar Gamble: The Ambitious Quest to Build Its Own Space‑Ready GPU

Mar 25, 2026 · Industry Insights

Why Meta Jumped on Arm’s First In‑House Neoverse Chip

Arm has shifted from pure IP licensing to launching its own Neoverse processor, securing Meta as the first customer, a move that could reshape semiconductor power dynamics by compressing the value chain and intensifying competition among chip designers and server manufacturers.

AI computeARMMeta

0 likes · 7 min read

Why Meta Jumped on Arm’s First In‑House Neoverse Chip

Aug 17, 2025 · Fundamentals

From Specification to Silicon: The Complete Digital Chip Design Flow

This article provides a comprehensive, step‑by‑step overview of digital chip design, covering specification definition, system architecture, front‑end logic design, back‑end physical implementation, verification, sign‑off, and tape‑out, complete with diagrams and practical insights into each stage.

Digital ICEDATape-out

0 likes · 21 min read

From Specification to Silicon: The Complete Digital Chip Design Flow

Open Source Linux

Jul 16, 2025 · Artificial Intelligence

How Huawei’s New AI Chip Aims to Rival Nvidia and AMD GPUs

Huawei is developing a new AI‑focused GPU‑style chip that mirrors Nvidia and AMD architectures, aiming to ease Chinese developers’ shift from Nvidia hardware, but still faces software compatibility hurdles due to reliance on CUDA and ongoing U.S. export restrictions.

AI ChipCUDAGPU

0 likes · 3 min read

How Huawei’s New AI Chip Aims to Rival Nvidia and AMD GPUs

Architects' Tech Alliance

Jul 3, 2025 · Artificial Intelligence

What Makes ASIC Chips the Powerhouse Behind AI? A Deep Dive

This article explains what ASIC chips are, how they differ from CPUs, GPUs and FPGAs, classifies them by customization level and function, outlines their performance and cost advantages, discusses their drawbacks, and reviews current products and market trends driving AI hardware adoption.

AI hardwareASICFPGA

0 likes · 11 min read

What Makes ASIC Chips the Powerhouse Behind AI? A Deep Dive

Jun 20, 2025 · Artificial Intelligence

Is China Only Two Years Behind the US in AI Chips? Insights from the US CTO

US CTO David Sachs warned that China’s AI and semiconductor capabilities are merely one to two years behind the United States, highlighting Huawei’s rapid progress in GPU design, the potential impact of export controls, and the broader implications for global tech competition.

AI hardwareHuaweiUS-China tech rivalry

0 likes · 5 min read

Is China Only Two Years Behind the US in AI Chips? Insights from the US CTO

Architects' Tech Alliance

Dec 29, 2024 · Industry Insights

Why Broadcom’s $1T Valuation Signals a New Era for AI ASICs

Broadcom’s market‑cap breakthrough past $1 trillion highlights its strategic push into AI ASICs, revealing how ASIC‑FPGA trade‑offs, collaborations with Google, and competition with Nvidia’s GPU ecosystem are reshaping the high‑performance computing landscape.

AI ASICBroadcomFPGA

0 likes · 13 min read

Why Broadcom’s $1T Valuation Signals a New Era for AI ASICs

Architects' Tech Alliance

Jun 17, 2024 · Industry Insights

What Drives the Evolution of Ethernet Switches? From Core to White‑Box

This article provides a comprehensive overview of Ethernet switches, covering their definitions, multiple classification dimensions, architectural roles in campus, enterprise, and data‑center scenarios, component makeup, market dynamics between black‑box and white‑box solutions, and future trends in switch chip development.

Ethernet SwitchWhite-box Switchchip design

0 likes · 11 min read

What Drives the Evolution of Ethernet Switches? From Core to White‑Box

Java Tech Enthusiast

Jun 7, 2024 · Fundamentals

Engineer Builds GPU from Scratch in Two Weeks

In just two weeks, engineer Adam Majmudar designed and implemented a minimalist GPU called tiny‑gpu—complete with a custom 11‑instruction ISA, Verilog RTL, and verified via OpenLane—sharing the open‑source project on GitHub, earning thousands of stars, and preparing it for fabrication through Tiny Tapeout 7, showcasing how modern tools make DIY chip design increasingly accessible.

EDAGPUMachine Learning

0 likes · 8 min read

Engineer Builds GPU from Scratch in Two Weeks

Architects' Tech Alliance

Jan 27, 2024 · Industry Insights

What Makes ASIC Chips Different? A Deep Dive into Types, Benefits, and Market Trends

This article provides a comprehensive overview of ASIC chips, covering their definition, material composition, classification by customization level and application, key advantages and drawbacks, notable product examples, and emerging market opportunities across AI, edge computing, and consumer electronics.

ASICHardwarechip design

0 likes · 11 min read

What Makes ASIC Chips Different? A Deep Dive into Types, Benefits, and Market Trends

Architects' Tech Alliance

Jul 12, 2023 · Industry Insights

Why AMD’s VP1902 Is the World’s Largest FPGA and What It Means for Chip Design

AMD’s new Versal Premium VP1902 FPGA, the world’s largest adaptive SoC, doubles logic capacity over its predecessor, adds extensive high‑speed transceivers, NoC and PCIe upgrades, and promises faster debugging and AI‑driven chip validation, marking a significant shift in semiconductor prototyping.

AMDAdaptive SoCFPGA

0 likes · 8 min read

Why AMD’s VP1902 Is the World’s Largest FPGA and What It Means for Chip Design

Jun 30, 2023 · Artificial Intelligence

How AI Created the World’s First Fully Autonomous CPU – Qǐ Méng 1

Chinese researchers used generative AI to design Qǐ Méng 1, the first completely self‑generated CPU chip that runs Linux and rivals early Intel 486 performance, showcasing the rapid rise of AI‑driven semiconductor design.

AICPURISC-V

0 likes · 4 min read

How AI Created the World’s First Fully Autonomous CPU – Qǐ Méng 1

Aug 16, 2022 · Fundamentals

How US Export Controls on Advanced EDA Tools Could Reshape China's Chip Industry

The U.S. added cutting‑edge electronic design automation (EDA) software and related semiconductor technologies to its export control list, prompting concerns about short‑term disruptions and long‑term constraints on China's advanced chip design while also spurring domestic EDA development.

ChinaEDAExport controls

0 likes · 9 min read

How US Export Controls on Advanced EDA Tools Could Reshape China's Chip Industry

Architects' Tech Alliance

Aug 10, 2022 · Industry Insights

FPGA vs ASIC: In‑Depth Technical Comparison for AI and High‑Performance Computing

This article provides a detailed, line‑by‑line analysis of a chart comparing FPGA and ASIC across dimensions such as upfront costs, unit cost, time‑to‑market, performance, power consumption, field updates, density, design flow, granularity, verification needs, upgrade paths, and additional features, helping engineers decide which technology best fits their high‑performance AI workloads.

AI acceleratorsASICFPGA

0 likes · 12 min read

FPGA vs ASIC: In‑Depth Technical Comparison for AI and High‑Performance Computing

Baidu Tech Salon

Jun 28, 2022 · Artificial Intelligence

How Kunlun XPU‑R Redefines AI Compute: Architecture, Performance, and Future Trends

The article presents a detailed technical review of Kunlun Chip's XPU‑R AI accelerator, covering its evolution from early FPGA prototypes to the current 7nm, 256 TOPS chip, the architectural choices that address AI workload demands, performance advantages over CPUs/GPUs, and the product ecosystem supporting diverse AI scenarios.

AI accelerationAI hardwareKunlun chip

0 likes · 20 min read

How Kunlun XPU‑R Redefines AI Compute: Architecture, Performance, and Future Trends

Baidu Tech Salon

Jun 13, 2022 · Artificial Intelligence

Kunlun Core AI Chips: Making Computing Smarter

The 2022 Beijing Zhiyuan Conference report by Kunlun Core’s chip R&D director outlines AI chip market opportunities and challenges, describes the company’s shift from FPGA clusters to a programmable XPU‑R architecture with 7nm, 256 TOPS INT8 performance, GDDR6 memory and PCIe 4.0, and details current deployments and plans for third‑ and fourth‑generation chips.

AI ChipAI acceleratorGDDR6

0 likes · 12 min read

Kunlun Core AI Chips: Making Computing Smarter

Tencent Architect

Jun 9, 2022 · Artificial Intelligence

From Zero to Chip: Tencent’s Multi‑Year Journey in AI, FPGA, and Smart‑NIC Development

Tencent’s hardware teams evolved from a lack of verification tools in 2019 to building AI inference chips, video‑encoding silicon, and intelligent NICs, overcoming FPGA challenges, scaling cloud infrastructure, and delivering high‑performance, low‑cost solutions for massive multimedia and AI workloads.

AI inferenceFPGASmart NIC

0 likes · 16 min read

From Zero to Chip: Tencent’s Multi‑Year Journey in AI, FPGA, and Smart‑NIC Development

IT Services Circle

Apr 8, 2022 · Fundamentals

The Rise of Domestic GPUs in China: IP Licensing, Imagination Technologies, and Market Dynamics

Chinese domestic GPU development has accelerated rapidly, driven by fast‑track product launches, strategic IP licensing from firms like Imagination Technologies, and supportive policies, while industry players navigate challenges of patents, design complexity, and market competition to bring full‑function GPUs to market.

ChinaGPUHardware

0 likes · 12 min read

The Rise of Domestic GPUs in China: IP Licensing, Imagination Technologies, and Market Dynamics

IT Services Circle

Mar 30, 2022 · Fundamentals

Apple’s Ongoing Battle with Heat: From the 2013 Mac Pro to the Self‑Designed M1 Chip

The article traces Apple’s four‑decade struggle with thermal challenges in its Mac lineup, recounting the legacy of the 2013 “trash‑can” Mac Pro, the evolution of chip architecture, and how the company’s shift to self‑designed silicon like the M1 series finally broke the heat‑constraint cycle.

AppleHardwareM1

0 likes · 13 min read

Apple’s Ongoing Battle with Heat: From the 2013 Mac Pro to the Self‑Designed M1 Chip

Architects' Tech Alliance

Mar 10, 2022 · Fundamentals

Why RISC‑V Is Succeeding: Open Architecture, Freedom, and Market Forces

The article explains how RISC‑V’s open, customizable ISA, the shift toward free and unrestricted hardware design, and market pressures such as Moore’s law slowdown and AI‑driven compute demand together fuel its rapid adoption, ecosystem growth, and competitive edge over proprietary architectures.

Hardware InnovationOpen ISARISC-V

0 likes · 11 min read

Why RISC‑V Is Succeeding: Open Architecture, Freedom, and Market Forces

Architects' Tech Alliance

Feb 7, 2022 · Cloud Computing

Pathways and Strategies for Migrating EDA Design Environments to the Cloud

This article outlines the methodology, key decision factors, and practical scenarios for moving electronic design automation (EDA) environments to the cloud, comparing hybrid and full‑cloud solutions for large design firms and start‑ups, and presents case studies such as STA migration.

Cloud ComputingEDAFull Cloud

0 likes · 15 min read

Pathways and Strategies for Migrating EDA Design Environments to the Cloud

Architects' Tech Alliance

Aug 30, 2021 · Industry Insights

What You Need to Know About ASIC Chips: Types, Benefits, and Market Outlook

This article provides a comprehensive overview of ASIC chips, covering their definition, hardware composition, classification by customization and function, key advantages and drawbacks, notable product examples, and emerging market trends driving growth across AI, security, and consumer electronics.

ASICHardwareIndustry Insights

0 likes · 11 min read

What You Need to Know About ASIC Chips: Types, Benefits, and Market Outlook

Aug 10, 2021 · Fundamentals

Why Tech Giants Are Racing to Build Their Own Chips – The New Semiconductor Arms Race

Amid global chip shortages and shifting market dynamics, Chinese internet powerhouses like ByteDance, Tencent, and Xiaomi, alongside global players such as Google, Intel, and Nvidia, are accelerating their own semiconductor initiatives, reshaping the industry from smartphone SoCs to AI‑focused cloud processors.

AI chipsARM architectureCloud Computing

0 likes · 14 min read

Why Tech Giants Are Racing to Build Their Own Chips – The New Semiconductor Arms Race

Architects' Tech Alliance

Jul 16, 2021 · Artificial Intelligence

AI Chip Landscape: GPUs, FPGAs, and ASICs for Deep Learning

The article explains how artificial intelligence relies on algorithms, compute and data, compares engineering and simulation methods, and details the roles, architectures, performance and energy characteristics of GPUs, FPGAs, and ASICs as the primary hardware accelerators for modern deep‑learning applications.

ASICArtificial IntelligenceFPGA

0 likes · 14 min read

AI Chip Landscape: GPUs, FPGAs, and ASICs for Deep Learning

Architects' Tech Alliance

Apr 2, 2021 · Fundamentals

MIPS Open Instruction Set (Release 6) Initiative and Comparison with RISC‑V

The article outlines Wave Computing’s 2018 decision to open the MIPS Release 6 instruction set, describes the evolution and product lines of MIPS, compares the open‑source licensing and ecosystem of MIPS with RISC‑V, and discusses market adoption, commercial models, and future challenges.

Instruction Set ArchitectureMIPSOpen ISA

0 likes · 9 min read

MIPS Open Instruction Set (Release 6) Initiative and Comparison with RISC‑V

Architects' Tech Alliance

Mar 10, 2021 · Industry Insights

Why RISC‑V Is Shaping the Future of Custom Chips in China and Beyond

The article analyzes RISC‑V’s open, modular ISA, its technical advantages over legacy architectures, the rapidly maturing global and Chinese ecosystems, real‑world applications, and strategic recommendations for China to build an independent, competitive semiconductor industry amid trade tensions and policy drives.

AI hardwareChina technology policyIoT

0 likes · 10 min read

Why RISC‑V Is Shaping the Future of Custom Chips in China and Beyond

Architects' Tech Alliance

Jan 24, 2021 · Fundamentals

RISC‑V Instruction Set Architecture: Background, Technical Features, Ecosystem, and Industry Applications

The article provides a comprehensive overview of RISC‑V, covering its origins amid trade‑war pressures, open‑source technical characteristics, growing global and Chinese ecosystem, comparisons with ARM and x86, and its emerging role in low‑power, customizable chips for IoT and AI applications.

AIInstruction Set ArchitectureIoT

0 likes · 10 min read

RISC‑V Instruction Set Architecture: Background, Technical Features, Ecosystem, and Industry Applications

Architects' Tech Alliance

Dec 21, 2020 · Fundamentals

RISC‑V Architecture: History, Advantages, and Emerging Applications

The article provides a comprehensive overview of the open‑source RISC‑V instruction set, its historical development, technical benefits such as modularity and a minimal instruction set, and its growing relevance across IoT, mobile, server, storage, AI, and security domains, while also discussing ecosystem challenges and industry initiatives.

CPU architectureIoTOpen Source

0 likes · 12 min read

RISC‑V Architecture: History, Advantages, and Emerging Applications

Open Source Linux

Oct 19, 2020 · Artificial Intelligence

How Huawei Built a Multi‑Series Chip Empire: From AI to 5G

This article offers a comprehensive overview of Huawei's three‑decade chip development, detailing the evolution of its AI, computing, mobile SoC, 5G communication, IoT, and video chips, their technical specifications, market impact, and future roadmap within China's semiconductor landscape.

5GAIHuawei

0 likes · 15 min read

How Huawei Built a Multi‑Series Chip Empire: From AI to 5G

IT Architects Alliance

Oct 4, 2020 · Industry Insights

How Huawei Built a Five‑Series Chip Empire: From 1991 to AI Powerhouses

This article traces Huawei’s three‑decade journey from its modest 1991 chip beginnings to a diversified portfolio of five major series—Kirin, Kunpeng, Ascend, Balong/Tiangang, Boudica/Lingxiao, and Honghu—detailing their technical evolution, market impact, and future roadmap across mobile, compute, AI, 5G, IoT, and video domains.

5GAIHuawei

0 likes · 18 min read

How Huawei Built a Five‑Series Chip Empire: From 1991 to AI Powerhouses

Aug 9, 2020 · Fundamentals

How Five Undergraduates Designed a 64‑bit RISC‑V Chip and Graduated with Their Own Processor

Five 2016‑class undergraduates from the University of Chinese Academy of Sciences completed a 64‑bit RISC‑V SoC chip named "NutShell," successfully fabricated it in 110 nm, ran Linux and a custom teaching OS, and presented the open‑source design at the RISC‑V Global Forum, showcasing a novel "One Life One Chip" education model.

RISC-VSOCchip design

0 likes · 19 min read

How Five Undergraduates Designed a 64‑bit RISC‑V Chip and Graduated with Their Own Processor

Jan 3, 2020 · Industry Insights

What Are Alibaba DAMO Academy’s 2020 Tech Trend Predictions and Their Implications?

Alibaba's DAMO Academy outlines ten disruptive technology trends for 2020—including AI’s shift to cognitive intelligence, compute‑storage integration, industrial‑Internet hyper‑convergence, massive machine collaboration, modular chip design, mass‑scale blockchain, quantum computing breakthroughs, new semiconductor materials, privacy‑preserving AI, and cloud‑centric innovation—offering a comprehensive outlook on the next wave of digital transformation.

AIBlockchainCloud Computing

0 likes · 11 min read

What Are Alibaba DAMO Academy’s 2020 Tech Trend Predictions and Their Implications?

Xianyu Technology

Jan 2, 2020 · Industry Insights

Top 10 Tech Trends of 2020: AI, Quantum, Blockchain, and Beyond

The 2020 DAMO Academy report outlines ten transformative technology trends—including the shift from perceptual to cognitive AI, compute‑storage integration, industrial‑internet hyper‑convergence, large‑scale multi‑agent collaboration, modular chip design, mass‑market blockchain, quantum‑computing breakthroughs, new semiconductor materials, privacy‑preserving AI, and cloud as the core of IT innovation—highlighting their potential impact on the next decade of tech development.

AIBlockchainCloud Computing

0 likes · 10 min read

Top 10 Tech Trends of 2020: AI, Quantum, Blockchain, and Beyond

Architects' Tech Alliance

Jul 27, 2019 · Fundamentals

A Comprehensive Overview of Chip Design Process and EDA Toolchain

The article provides a detailed, English-language overview of the entire integrated circuit design flow—from architecture and algorithm selection through RTL coding, verification, synthesis, layout, and sign‑off—highlighting the roles, tools, and challenges faced by engineers in modern ASIC and FPGA development.

ASICEDAFPGA

0 likes · 29 min read

A Comprehensive Overview of Chip Design Process and EDA Toolchain