Huawei’s τ (Tao) Scaling Theory: How Time‑Based Chip Design Breaks Performance Limits

Background and Motivation

On May 25, 2026, Huawei HiSilicon chief He Tingbo published the paper “Multi‑Layer Electronic System Time‑Scaling Theory”, introducing the τ (Tao) scaling theory. The author argues that after six decades of performance gains driven by geometric scaling, the semiconductor industry faces physical limits (2 nm, 1 nm nodes), soaring costs, and diminishing returns, while AI, autonomous driving, and large‑model workloads demand ever‑higher compute.

τ (Time Constant) Scaling Theory

The core idea is to replace size‑based optimisation with time‑based optimisation. τ, the time constant, becomes the single metric for transistor switching (picoseconds), chip signal transmission, server computation, and data‑center task scheduling (seconds). The theory decomposes a chip into four layers—device, circuit, chip, and system—each targeting “shortening τ”. This unified metric creates a common language for process, design, and architecture engineers and assigns scenario‑specific acceleration factors (mobile ≈ 1.3×, autonomous driving ≈ 1.5×, AI ≈ 10×).

Evidence from Huawei’s Product Line

Huawei claims that six years of development across 381 mass‑produced chips have validated the theory. Two concrete breakthroughs are highlighted:

Mobile SoC – LogicFolding : By vertically stacking digital, analog, and memory circuits (logic folding), performance is increased without further node shrinkage. Transistor density rises from 155 MTr/mm² to 238 MTr/mm² (+55%), equivalent to three years of geometric scaling. Performance‑per‑watt improves by 41%, core frequency reaches 3.1 GHz (+13%), SRAM frequency rises 40%, and clock buffers are halved with 25% reduced clock skew and 30% shorter interconnects.

AI Data‑Center – Unified Memory‑Semantic Bus + Hi‑ONE Optical I/O + 3D Folding : A single protocol replaces multiple stack layers, cutting remote‑access latency from tens of microseconds to 100 ns (τ reduced by 500×). The optical engine delivers 8 Tb/s per module, shrinking intra‑chip transmission distance from 100 cm to 5 cm and extending cross‑rack communication from 1 m to 100 m. 3D folding moves memory, I/O, and power vertically, turning performance growth into a square‑law with core count.

Roadmap and Outlook

Huawei’s roadmap projects a 2029 CPU clock speed exceeding 4 GHz and a 2035 transistor density surpassing 400 MTr/mm², effectively achieving a 1.4 nm equivalent performance level without the need for the most advanced EUV lithography. The τ scaling theory is positioned as the first unified optimisation framework after Dennard scaling, redefining “advanced chip” by time rather than feature size.

Challenges

Key challenges remain: EDA tools must be rewritten to support time‑centric optimisation, and wafer‑process variations need to be addressed. Nevertheless, the 381‑chip production record demonstrates that τ scaling has moved from theory to a practical, large‑scale implementation.

Conclusion

As Moore’s law reaches its physical wall, Huawei’s τ (Tao) scaling theory offers a new “high‑speed” pathway, emphasizing time compression over size reduction to sustain chip performance growth in the post‑Moore era.