Huawei introduced the “τ (Tau) Law” at ISCAS 2026, proposing a shift from geometric scaling to time‑constant reduction to overcome the physical limits of Moore’s Law, and outlines how signal‑propagation delay can be compressed through system‑level innovations such as logical folding and advanced packaging.
Huawei introduced the “τ (Tau) Law” at the 2026 ISC conference, proposing a shift from geometric scaling of Moore’s law to “time miniaturization” that reduces signal propagation delay through logical folding and interconnect redesign, aiming to sustain semiconductor performance as transistor sizes near physical limits.
Huawei’s new τ (Tao) scaling theory shifts chip optimisation from shrinking dimensions to compressing time, offering a post‑Moore roadmap that boosts mobile SoC density by 55%, AI data‑center latency by 500×, and promises continued performance growth without relying on advanced EUV lithography.
Huawei’s He Tingbo announced at ISCAS 2026 that Moore’s geometric scaling has reached a physical ceiling and introduced the “Tau Law,” a time‑scaling strategy that leverages multi‑layer optimization, logic folding, and the Lingqu bus to achieve 1.4 nm‑equivalent performance without EUV, outlining a roadmap to 2026 and 2031.
The article introduces Huawei’s “τ Law”, which shifts chip advancement from geometric scaling to time‑constant reduction, explains its four‑layer optimization (device, circuit, chip, system), showcases logic‑folding technology, and outlines a roadmap that could match 1.4 nm performance by 2031 without relying on EUV lithography.
The article examines how, as Moore's Law ends, performance gains will increasingly rely on software optimization, algorithmic advances, and hardware architecture innovations, illustrated by matrix multiplication benchmarks and discussions of Dennard scaling, parallelism, and emerging technologies.
With Moore's Law reaching its limits, a recent Science paper by MIT, Nvidia, and Microsoft researchers argues that future computing performance will rely on improvements in the software stack, algorithmic innovations, and hardware architecture, as demonstrated by performance engineering benchmarks and evolving hardware trends.
The article surveys recent digital‑infrastructure trends, explaining why traditional Moore's Law scaling is slowing, describing More‑Moore and Beyond‑CMOS approaches, and detailing new chip architectures such as DSA, 3D stacking, Chiplet, compute‑in‑memory, and distributed xPU‑centric systems that together address the growing compute demands of AI, AR/VR, and bio‑pharma workloads.
The article explains how slowing transistor cost reductions and Moore's law have driven the emergence of Chiplet technology, detailing its cost and yield advantages, rapid market growth, and the role of advanced packaging methods such as 3D Fabric, EMIB, and X‑Cube in enabling heterogeneous integration.
This article outlines eight enduring ideas—from designing for Moore's Law and using abstraction to speeding up common cases, leveraging parallelism, pipelining, prediction, memory hierarchy, and redundancy—that have shaped computer architecture over the past six decades.
In the post‑Moore’s‑law era, CPU performance gains have slowed, prompting a detailed analysis of three governing laws, the rise of domain‑specific architectures, and key optimization techniques such as reducing data movement, lowering precision, and increasing parallelism to guide future processor design.
The article examines the end of Moore's Law, the rapid growth of cloud computing, the challenges of virtualization overhead, and how Alibaba's Shenlong architecture leverages hardware acceleration to revive performance gains and reshape the future of hardware‑software co‑evolution.
The article explains why learning to identify emerging technologies is crucial, outlines the historical waves of internet innovation, lists common reasons for tech failures and successes, and highlights Moore's law as the underlying driver of technological adoption.
