Post‑Moore’s Law CPU Performance: Laws, Domain‑Specific Architectures, and Optimization Strategies

The article, authored by Bao Yungang, a researcher at the Chinese Academy of Sciences, reviews why CPU performance improvements have plateaued after Moore's law and examines three historic laws that have shaped computer architecture: Moore's law, Makimoto's law, and Bell's law.

It highlights that despite transistor count growth, most software cannot fully exploit hardware capabilities, leading to massive performance gaps between naïve implementations (e.g., Python) and highly tuned code that leverages architecture features.

Domain‑Specific Architecture (DSA) is presented as a primary solution: by customizing micro‑architectures for particular workloads, designers can achieve orders‑of‑magnitude gains in performance‑per‑watt, effectively embedding expert programmer knowledge into hardware.

The discussion then outlines three major optimization directions driven by the three laws: (1) reducing data movement through instruction‑set design, cache optimization, and memory‑compression techniques; (2) lowering data precision, especially for AI workloads where 16‑bit or 8‑bit formats can replace 64‑bit floating point without significant accuracy loss; (3) increasing parallelism at multiple levels, from instruction‑level to thread‑level and accelerator‑level parallelism.

Concrete examples include specialized accelerators for TCP/IP L5 protocols, video‑transcoding hardware in data centers, Intel’s cache and memory‑access improvements, and emerging floating‑point formats like POSIT that simplify precision scaling.

The article concludes that DSA will dominate near‑future CPU design and that architects should focus on the three optimization routes—data‑movement reduction, precision reduction, and parallelism enhancement—to meet the demands of the emerging AIoT era.