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CPU architecture

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Architects' Tech Alliance
Architects' Tech Alliance
Jun 9, 2025 · Fundamentals

How Do x86, ARM, and RISC‑V Architectures Differ? A Deep Dive into CPU Instruction Sets

This article compares the major CPU instruction set architectures—x86, ARM, and RISC‑V—detailing their design philosophies, evolution, strengths, and weaknesses, while also summarizing recent updates in CPU, GPU, memory, and storage technologies and highlighting the trade‑offs between CISC and RISC approaches.

ARMCISCCPU architecture
0 likes · 12 min read
How Do x86, ARM, and RISC‑V Architectures Differ? A Deep Dive into CPU Instruction Sets
Architects' Tech Alliance
Architects' Tech Alliance
May 25, 2025 · Fundamentals

Comprehensive Overview of Shenwei (申威) Chip Development, Technology, Roadmap, and Applications

This article provides an in‑depth overview of Shenwei chips, covering their development history, core technical advantages such as a self‑designed instruction set and high‑performance computing capabilities, the current product line‑up, and their applications in supercomputing, cloud data centers, security, and embedded systems.

CPU architectureHardware fundamentalsHigh Performance Computing
0 likes · 13 min read
Comprehensive Overview of Shenwei (申威) Chip Development, Technology, Roadmap, and Applications
IT Services Circle
IT Services Circle
May 11, 2025 · Fundamentals

Why Software Can Run Across Different CPU Architectures and Operating Systems: Rosetta, Universal Binaries, and Compatibility Techniques

The article explains why software copied between Windows and macOS or between Intel‑based and ARM‑based Macs may or may not run, covering CPU instruction set incompatibility, OS API differences, and the translation or packaging solutions such as Rosetta, Universal Binaries, Wine, compilers, and virtual machines.

CPU architectureRosettaUniversal Binary
0 likes · 9 min read
Why Software Can Run Across Different CPU Architectures and Operating Systems: Rosetta, Universal Binaries, and Compatibility Techniques
Deepin Linux
Deepin Linux
Mar 27, 2025 · Fundamentals

Understanding Linux Memory Barriers: Concepts, Types, and Implementation

This article explains why modern multi‑core CPUs need memory barriers, describes the different kinds of barriers (full, read, write), shows how they are implemented in the Linux kernel and hardware, and illustrates their use in multithreaded and cache‑coherent programming.

CPU architectureCache CoherenceLinux Kernel
0 likes · 41 min read
Understanding Linux Memory Barriers: Concepts, Types, and Implementation
Deepin Linux
Deepin Linux
Nov 12, 2024 · Fundamentals

Understanding Linux Memory Barriers: Types, Usage, and Implementation

This article provides a comprehensive overview of Linux memory barriers, explaining why they are needed for correct ordering of memory operations on modern multi‑core CPUs, describing the different barrier types (read, write, full), their implementation in the kernel and Java, and illustrating their use in synchronization primitives and lock‑free data structures with code examples.

CPU architectureLinux KernelSynchronization
0 likes · 71 min read
Understanding Linux Memory Barriers: Types, Usage, and Implementation
Architects' Tech Alliance
Architects' Tech Alliance
Oct 13, 2024 · Fundamentals

Overview of Huawei Kunpeng 920 Processor Architecture and Subsystems

The article provides a detailed technical overview of Huawei's Kunpeng 920 processor, describing its ARM‑based RISC architecture, chip organization, core and cluster layout, security features, IMU management, and the various subsystems such as IO, interrupt, network, SAS, and PCIe.

CPU architectureKunpengRISC
0 likes · 12 min read
Overview of Huawei Kunpeng 920 Processor Architecture and Subsystems
Refining Core Development Skills
Refining Core Development Skills
Aug 5, 2024 · Fundamentals

Deep Dive into Linux Processes and Memory: A Comprehensive Guide

This article introduces a new book 'Deep Understanding of Linux Processes and Memory' that systematically explains CPU, memory, and process scheduling principles, covering hardware fundamentals, virtual memory, Golang coroutines, container resource management, and performance optimization techniques.

CPU architectureContainersLinux
0 likes · 5 min read
Deep Dive into Linux Processes and Memory: A Comprehensive Guide
Refining Core Development Skills
Refining Core Development Skills
Jan 3, 2024 · Fundamentals

Understanding Intel Xeon Server CPU Naming Rules, Generations, and Architecture

This article explains the Intel Xeon server CPU naming conventions, outlines each generation from Skylake to Sapphire Rapids, and details the internal Mesh interconnect and external UPI bus that enable high‑core counts and multi‑CPU scalability in modern data‑center processors.

CPU architectureIntelMesh Interconnect
0 likes · 12 min read
Understanding Intel Xeon Server CPU Naming Rules, Generations, and Architecture
JD Retail Technology
JD Retail Technology
Dec 19, 2023 · Fundamentals

Overview of CPU Architecture, Performance Trends, and Their Impact on Software Development

This article reviews recent decades of CPU performance improvements and semiconductor process advances, explains current CPU architectures, instruction set evolution, and how these trends influence software development practices, including parallelism, SIMD, multithreading, and power‑efficiency considerations.

CPU architectureInstruction setMicroarchitecture
0 likes · 42 min read
Overview of CPU Architecture, Performance Trends, and Their Impact on Software Development
Architects' Tech Alliance
Architects' Tech Alliance
Dec 7, 2023 · Artificial Intelligence

Evolution of ARM Architecture: From EPYC Flexibility to Armv9, Neoverse, Graviton and Confidential Compute

The article provides a comprehensive overview of ARM's recent architectural advances—including the flexible EPYC design, the Neoverse platform, AWS Graviton processors, and the security‑focused Armv9 with AI‑optimized SVE2 and Confidential Compute—highlighting their impact on cloud, data‑center and edge computing.

ARMArtificial IntelligenceCPU architecture
0 likes · 18 min read
Evolution of ARM Architecture: From EPYC Flexibility to Armv9, Neoverse, Graviton and Confidential Compute
Architects' Tech Alliance
Architects' Tech Alliance
Nov 22, 2023 · Fundamentals

Understanding ARM vs. x86 Processors, RISC vs. CISC, and Their Energy Trade‑offs

The article explains the fundamental differences between ARM and x86 CPUs, compares RISC and CISC instruction set philosophies, discusses how each architecture balances transistor count, performance, power consumption and cost, and highlights why ARM dominates low‑power devices while x86 remains prevalent in high‑performance computers.

ARMCISCCPU architecture
0 likes · 9 min read
Understanding ARM vs. x86 Processors, RISC vs. CISC, and Their Energy Trade‑offs
Architects' Tech Alliance
Architects' Tech Alliance
Oct 9, 2023 · Fundamentals

UCIe and CXL: Emerging Standards for Chiplet Interconnect and Memory Expansion

The article examines the rise of chiplet technology, the UCIe interconnect standard, and CXL‑based memory expansion, analyzing technical specifications, scalability challenges of CPU memory channels, and future prospects of CXL 2.0 and 3.0 for server and cloud architectures.

CPU architectureCXLChiplet
0 likes · 11 min read
UCIe and CXL: Emerging Standards for Chiplet Interconnect and Memory Expansion
Architects' Tech Alliance
Architects' Tech Alliance
Sep 12, 2023 · Fundamentals

Rise of ARM Servers in China: Market Share, Trends, and Implications

The recent CITIC Bank procurement reveals that ARM servers now dominate Chinese data‑center purchases, accounting for 77% of server spend, while global ARM server share is growing rapidly despite x86's historic dominance, driven by cost, performance‑per‑watt advantages and geopolitical constraints.

ARMCPU architectureServer
0 likes · 7 min read
Rise of ARM Servers in China: Market Share, Trends, and Implications
OPPO Kernel Craftsman
OPPO Kernel Craftsman
Jul 7, 2023 · Fundamentals

Analysis of Arm's 2023 Cortex‑X4, A720, and A520 Microarchitectures

Arm’s 2023 processor lineup—Cortex‑X4, A720, and A520—introduces a 15% performance boost, 20‑22% efficiency gains, a 64‑bit‑only Armv9.2 ISA with QARMA3 PAC, larger caches, expanded decode and execution resources, and a DSU120 module supporting up to 14 cores and 32 MiB L3.

A520A720ARM
0 likes · 14 min read
Analysis of Arm's 2023 Cortex‑X4, A720, and A520 Microarchitectures
Architects' Tech Alliance
Architects' Tech Alliance
Mar 8, 2023 · Fundamentals

Overview of ARMv8 Architecture and the Transition from 32‑bit to 64‑bit

This article provides a comprehensive overview of the ARMv8 architecture, describing its 32‑bit (AArch32) and 64‑bit (AArch64) execution states, the benefits of larger registers and address spaces, and detailed specifications of Cortex‑A53, Cortex‑A57, and Cortex‑A73 processors.

64-bitARMv8Aarch64
0 likes · 16 min read
Overview of ARMv8 Architecture and the Transition from 32‑bit to 64‑bit
Architects' Tech Alliance
Architects' Tech Alliance
Mar 3, 2023 · Fundamentals

Arm Announces Armv9 Architecture: New Security, AI, and SVE2 Vector Extensions

Arm's newly unveiled Armv9 architecture, presented at Vision Day, introduces major enhancements across security, artificial intelligence, and scalable vector extensions (SVE2), while outlining a roadmap for future CPUs, performance gains, and the confidential compute architecture that reshapes trust boundaries in modern computing.

ARMArmv9Artificial Intelligence
0 likes · 13 min read
Arm Announces Armv9 Architecture: New Security, AI, and SVE2 Vector Extensions
OPPO Kernel Craftsman
OPPO Kernel Craftsman
Feb 3, 2023 · Fundamentals

Analysis of Armv9 Microarchitectures: A710, A715, and A510

The article examines Armv9’s A710, A715, and A510 cores, detailing their microarchitectural tweaks—branch predictor expansion, dispatch width changes, SVE2 support, and 64‑bit‑only design—while highlighting modest performance and energy gains, code‑compatibility shifts, and evolving core‑count configurations in modern Snapdragon and MediaTek SoCs.

ARMArmv9CPU architecture
0 likes · 21 min read
Analysis of Armv9 Microarchitectures: A710, A715, and A510
Tencent Cloud Developer
Tencent Cloud Developer
Aug 8, 2022 · Fundamentals

Deep Dive into Function Call Implementation: From Assembly to CPU Registers

This article thoroughly explains low‑level function call implementation, covering Intel and AT&T assembly syntax, the evolution of CPU registers from 16‑bit to 64‑bit x86, caller‑ and callee‑saved conventions, stack‑based to register‑based parameter passing, stack frame setup, and assembly representations of control structures.

CPU architectureCPU registersLow-level programming
0 likes · 23 min read
Deep Dive into Function Call Implementation: From Assembly to CPU Registers
Architects' Tech Alliance
Architects' Tech Alliance
Jun 10, 2022 · Cloud Computing

In‑Depth Analysis of AWS Graviton 3: Architecture, Performance, and Comparison with x86 Competitors

The article provides a comprehensive technical review of AWS’s Graviton 3 ARM server CPU, detailing its SVE support, branch prediction, front‑end, renamer, execution units, cache hierarchy, and performance comparisons with Neoverse N1, Intel Ice Lake, and AMD Zen 3, while discussing cloud‑centric design trade‑offs.

ARMCPU architectureCloud Computing
0 likes · 18 min read
In‑Depth Analysis of AWS Graviton 3: Architecture, Performance, and Comparison with x86 Competitors