Evolution of ARM Architecture: From EPYC Flexibility to Armv9, Neoverse, Graviton and Confidential Compute

ARM’s separation of CPU design and manufacturing has given AMD flexibility to choose processes for EPYC processors, helping it gain market share from Intel. Large‑scale users such as AWS and Alibaba Cloud prefer ARM because it offers more design autonomy.

The Neoverse platform, launched in 2011 with ARMv8‑A, provides a foundation for server‑grade CPUs. Early 64‑bit ARM CPUs (Cortex‑A53, A57) paved the way for later server products. In 2018 AWS previewed its first ARM server CPU, Graviton, based on the Cortex‑A72 (16 nm, 16 cores/threads). Graviton’s successor, Graviton2, uses the 7 nm Neoverse N1 (Cortex‑A76 derivative) and delivers over 30 % performance improvement, 64 cores, 300 billion transistors, 64 MiB L2 cache, DDR4‑3200 memory, and 2.5 GHz clock speed.

Graviton2 quickly became a dominant EC2 instance type, powering a wide range of general‑purpose, compute‑optimized and memory‑optimized instances, accounting for roughly half of AWS’s instance growth in 2020.

Armv9, announced in March 2021, builds on Armv8 with three main pillars: enhanced security, AI, and improved vector/DSP capabilities. It introduces SVE2 (Scalable Vector Extension 2), which expands vector lengths from 128 b to 2048 b, enabling a single binary to run efficiently across diverse hardware. SVE2 and new matrix‑multiply instructions target machine‑learning workloads.

The architecture also adds Confidential Compute Architecture (CCA), which creates hardware‑isolated “realms” that protect code and data from compromised operating systems or hypervisors. Memory Tagging Extensions (MTE), introduced in Armv8.5, further improve memory‑safety by detecting buffer overflows and use‑after‑free errors.

Future ARM roadmaps show continued performance gains for mobile (X1, Cortex‑A78 successors) and server (Neoverse V1, N2) designs, with expected IPC improvements of 30 % and continued emphasis on security, AI, and unified vector processing across devices.