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Architects' Tech Alliance
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Architects' Tech Alliance

Sharing project experiences, insights into cutting-edge architectures, focusing on cloud computing, microservices, big data, hyper-convergence, storage, data protection, artificial intelligence, industry practices and solutions.

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Latest from Architects' Tech Alliance

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Architects' Tech Alliance
Architects' Tech Alliance
May 31, 2026 · Industry Insights

Huawei AI Data Center Reference Design – Downloadable Blueprint

The Huawei AI Data Center Reference Design offers a standardized, integrated, high‑performance compute infrastructure for large‑model training and inference, built on GB/T 50174, featuring modular GPU/HBM servers, 20–50 kW per rack, leaf‑spine 100/200/400 Gbps networking, liquid cooling, redundant power, and intelligent management, with a downloadable package for replication.

AIData CenterGPU
0 likes · 4 min read
Huawei AI Data Center Reference Design – Downloadable Blueprint
Architects' Tech Alliance
Architects' Tech Alliance
May 30, 2026 · Industry Insights

Nine Domestic AI Chips Earn Top‑Tier Security Certification, Alibaba and Huawei Secure Two Slots Each

On May 26, 2026, China’s national security testing agencies certified nine domestic AI training and inference chips with the highest I‑level rating, turning AI chips into a mandatory procurement item for government, finance, telecom and energy sectors and reshaping the competitive landscape against foreign vendors.

AI chipsAlibabaBiren
0 likes · 8 min read
Nine Domestic AI Chips Earn Top‑Tier Security Certification, Alibaba and Huawei Secure Two Slots Each
Architects' Tech Alliance
Architects' Tech Alliance
May 28, 2026 · Industry Insights

How Huawei’s Kunpeng 960 Uses the τ Law and 3‑D Stacking to Defy Moore’s Law

Amid global semiconductor bottlenecks, Huawei’s Kunpeng line shifts from 2‑D planar CPUs to 3‑D stacked architectures, with the 950 introducing a two‑layer design and the upcoming 960 promising a three‑layer stack, 4 GHz clocks and a 54% performance boost, illustrating the τ scaling theory and a new supernode strategy that could reshape domestic and global server markets.

3D stackingCPU architectureHuawei
0 likes · 9 min read
How Huawei’s Kunpeng 960 Uses the τ Law and 3‑D Stacking to Defy Moore’s Law
Architects' Tech Alliance
Architects' Tech Alliance
May 27, 2026 · Industry Insights

Nvidia Vera CPU Smashes Intel and AMD x86 Titans in AI Workloads

Nvidia's Vera, an 88‑core custom ARM CPU designed for AI agents, delivers up to 55% higher overall performance than Intel Xeon 6980P, 10% over AMD EPYC 9575F and 63% over Nvidia Grace, while offering 1.2 TB/s LPDDR5X bandwidth, 500 W power envelope and a single‑chip design that could reshape the server CPU market.

AI serverARM CPULPDDR5X
0 likes · 10 min read
Nvidia Vera CPU Smashes Intel and AMD x86 Titans in AI Workloads
Architects' Tech Alliance
Architects' Tech Alliance
May 26, 2026 · Artificial Intelligence

Huawei Ascend 950 NPU Architecture Deep Dive – Full Whitepaper Inside

The article provides a detailed technical analysis of Huawei's Ascend 950 NPU series, covering its one‑chip dual‑structure for training and inference, SIMD/SIMT dual‑mode compute, ultra‑fine memory granularity, PD separation, native FP4 support, a high‑bandwidth 2.0 interconnect, and a fully self‑developed yet CUDA‑compatible ecosystem.

AI acceleratorAscend 950FP4
0 likes · 10 min read
Huawei Ascend 950 NPU Architecture Deep Dive – Full Whitepaper Inside
Architects' Tech Alliance
Architects' Tech Alliance
May 26, 2026 · Information Security

How Sugon Cloud’s “3D Secure Computation” Delivers Seamless Security for Financial Institutions

Facing the 2025‑2026 regulatory deadline, Sichuan Rural Commercial Union Bank migrated its core services to Sugon Cloud’s “3D Secure Computation” platform, achieving full‑link encryption with only a 4.4% performance overhead and proving that hardware‑based security can be both compliant and virtually invisible to users.

Performance OptimizationSugon Cloudcloud security
0 likes · 5 min read
How Sugon Cloud’s “3D Secure Computation” Delivers Seamless Security for Financial Institutions
Architects' Tech Alliance
Architects' Tech Alliance
May 25, 2026 · Industry Insights

Huawei’s τ (Tao) Scaling Theory: How Time‑Based Chip Design Breaks Performance Limits

Huawei’s new τ (Tao) scaling theory shifts chip optimisation from shrinking dimensions to compressing time, offering a post‑Moore roadmap that boosts mobile SoC density by 55%, AI data‑center latency by 500×, and promises continued performance growth without relying on advanced EUV lithography.

AI data centerHuaweiLogicFolding
0 likes · 8 min read
Huawei’s τ (Tao) Scaling Theory: How Time‑Based Chip Design Breaks Performance Limits
Architects' Tech Alliance
Architects' Tech Alliance
May 25, 2026 · Industry Insights

What Is the ‘τ Law’? How Huawei Aims to Reach 1.4 nm‑Level Performance in Five Years

The article introduces Huawei’s “τ Law”, which shifts chip advancement from geometric scaling to time‑constant reduction, explains its four‑layer optimization (device, circuit, chip, system), showcases logic‑folding technology, and outlines a roadmap that could match 1.4 nm performance by 2031 without relying on EUV lithography.

HuaweiMoore's LawSystem Optimization
0 likes · 9 min read
What Is the ‘τ Law’? How Huawei Aims to Reach 1.4 nm‑Level Performance in Five Years