What Is the ‘τ Law’? How Huawei Aims to Reach 1.4 nm‑Level Performance in Five Years

1. Moore’s Law and Its Limits

Moore’s Law, proposed in 1965, states that transistor counts double every 18‑24 months, driving performance through geometric scaling. After six decades of shrinking from 90 nm to 3 nm, the industry faces two insurmountable walls: a physical wall where transistors approach atomic dimensions, causing quantum tunnelling and leakage, and an economic wall where a 3 nm fab costs over $20 billion, limiting participation to a few giants.

2. The “τ Law”: Replacing “Shrinking Nanometers” with “Compressing Time”

The Greek letter τ denotes a time constant in physics, representing the basic delay for a signal to traverse a system. A smaller τ means faster signal propagation and more responsive systems. Huawei’s τ Law proposes “time‑scaling” – reducing signal latency across the entire chip stack instead of further shrinking transistors.

2.1 Analogy: From Packing Houses to Building Highways

Moore’s Law (geometric scaling): Build smaller, denser houses (transistors) to increase capacity.

τ Law (time scaling): Keep house size unchanged but construct highways, tunnels, and optimize traffic lights so that traffic (electrical signals) moves faster with less congestion.

2.2 Core Technology: Logic Folding

Traditional chips use a two‑dimensional planar layout, forcing signals to travel long, winding paths. Logic folding “folds” the planar circuit into a three‑dimensional structure, pulling distant modules physically closer, shortening critical paths, and cutting both latency and power consumption. Huawei announced that its next‑generation Kirin chip will be the first to fully integrate logic‑folding, delivering a performance leap.

3. Four‑Layer Collaborative Optimization

The τ Law is not a single technique but a hierarchy of optimizations spanning four layers:

Device layer: Optimize transistors, resistance, and parasitic capacitance to reduce fundamental signal delay.

Circuit layer: Apply logic folding to break planar constraints, lowering RC load and boosting density and performance.

Chip layer: Co‑design software, architecture, and silicon to precisely control instruction and data flows, increasing parallelism and eliminating idle cycles.

System layer: Deploy Huawei’s proprietary Lingqu bus and re‑engineered inter‑node protocols, enabling unified memory addressing and dramatically reducing inter‑chip communication latency (e.g., the Ascend 384 super‑node implementation).

4. Real‑World Validation

Huawei reports six years of practical experience, having mass‑produced 381 chip models across communications, terminals, automotive, and AI super‑computing scenarios using the τ‑Law methodology.

2026 Milestone: An upcoming Kirin chip will fully adopt logic folding, achieving a noticeable performance jump.

2031 Goal: Reach transistor density equivalent to a 1.4 nm process without EUV lithography, effectively matching the performance of the most advanced nodes.

5. Moore’s Law vs. τ Law: Complementary Relay

τ Law does not replace Moore’s Law; it hands the baton when geometric scaling stalls. Together, they form a relay: Moore’s Law drives spatial scaling, τ Law drives temporal scaling, jointly propelling chip evolution.

6. Broader Implications

The τ Law reflects a strategic shift for China’s semiconductor industry: rather than competing on ever‑smaller nodes, the focus moves to innovative system‑level time optimization, turning the “asymmetrical overtaking” concept into a practical roadmap.