What Is the ‘τ Law’? How Huawei Aims to Reach 1.4 nm‑Level Performance in Five Years
The article introduces Huawei’s “τ Law”, which shifts chip advancement from geometric scaling to time‑constant reduction, explains its four‑layer optimization (device, circuit, chip, system), showcases logic‑folding technology, and outlines a roadmap that could match 1.4 nm performance by 2031 without relying on EUV lithography.
