The Rise of RISC‑V: Open‑Source Instruction Set Architecture and Its Growing Adoption

Recently, Tesla joined the RISC‑V Foundation and is considering using the free RISC‑V design in its next‑generation chips, joining more than 100 other technology companies such as IBM, NXP, Western Digital, NVIDIA, Qualcomm, Samsung, Google, and Huawei.

The main reasons for this trend are the high licensing fees of ARM and the fully open nature of the RISC‑V instruction set, which many see as the "Linux of the CPU world". Early‑stage bets by many tech giants reflect confidence in RISC‑V's future.

Birth of RISC‑V

In 2010, a research team at the University of California, Berkeley began a project to design a new instruction set because existing ones (x86, ARM, MIPS, SPARC, PowerPC) were either proprietary or expensive. Within three months the team completed the first RISC‑V ISA, which was released publicly.

The first version contained fewer than 50 instructions, enough to implement a processor with fixed‑point arithmetic and privileged modes, while still allowing users to add custom instructions as needed.

The ISA was named RISC‑V, where "RISC" stands for Reduced Instruction Set Computer and "V" denotes the fifth generation, following four earlier Berkeley designs.

Crucially, the RISC‑V ISA is released under the permissive BSD license, allowing free use, modification, redistribution, and commercial exploitation without the restrictions of GPL‑licensed software.

Academic institutions find RISC‑V valuable; for example, researchers at the Chinese Academy of Sciences switched from Sun's OpenSPARC T1 and a closed‑source MicroBlaze to RISC‑V for a project, with results later used in Huawei's ARM‑based server CPUs.

RV12 RISC‑V Processor

Today, x86 and ARM dominate the CPU market, but both impose strict licensing and high fees. This creates an opening for RISC‑V, which is embraced by over a hundred companies and many universities worldwide.

India has also heavily invested in RISC‑V, funding projects such as the SHAKTI processor and a 2 GHz four‑core RISC‑V design, making the ISA a de‑facto national instruction set.

Berkeley’s Rocket chip, a 64‑bit out‑of‑order RISC‑V core, has been fabricated in 45 nm and 28 nm processes, achieving >1 GHz clock speeds, 10 % higher performance, 49 % better area efficiency, and 57 % lower dynamic power compared with an ARM Cortex‑A5.

Major companies such as Western Digital, NVIDIA, and the US DARPA are planning RISC‑V‑based solutions for storage, GPUs, aerospace, IoT, security, and server management, while the software ecosystem (toolchains, JVM, LLVM, Python, etc.) continues to mature.

The open, royalty‑free nature of RISC‑V makes it attractive for both academia and industry, promising widespread adoption similar to Linux’s success. However, the lack of a strong central authority raises concerns about potential fragmentation as vendors add proprietary extensions.

In summary, RISC‑V’s open‑source BSD license, low cost, and flexibility have driven rapid growth across research, education, and commercial sectors, but its future dominance will depend on how the community manages compatibility and governance challenges.