0 views collected around this technical thread.
This article compares the major CPU instruction set architectures—x86, ARM, and RISC‑V—detailing their design philosophies, evolution, strengths, and weaknesses, while also summarizing recent updates in CPU, GPU, memory, and storage technologies and highlighting the trade‑offs between CISC and RISC approaches.
The XiangShan open‑source RISC‑V processor, praised for its ARM‑level performance and detailed micro‑architecture, has sparked worldwide discussion after a George Hotz tweet, highlighting China’s systematic development of a high‑performance, community‑driven CPU project that began in 2019 and continues to evolve.
The article presents Flex‑RV, a sub‑dollar, bendable 32‑bit RISC‑V microprocessor built with IGZO TFT technology that integrates a programmable machine‑learning accelerator, achieves up to 60 kHz operation at less than 6 mW, and demonstrates reliable performance under mechanical stress for emerging wearable and smart‑packaging applications.
The 19th China Linux Kernel Developers Conference in Wuhan on October 26, 2024 attracted over 80,000 online viewers and nearly 400 developers, showcased five technical sub‑forums—from memory and storage I/O to virtualization and scheduling—featured AI‑focused kernel talks, announced a new open‑source innovation institute, and made all materials publicly available on GitHub.
This article provides a comprehensive overview of contemporary processor instruction set architectures, comparing CISC‑based x86 with RISC‑based ARM and RISC‑V, discussing their design philosophies, historical evolution, advantages, disadvantages, and the current landscape of domestic and international CPU development.
This article provides a comprehensive overview of modern processor instruction set architectures, comparing CISC‑based x86 with RISC‑based ARM and RISC‑V, discussing their historical development, design philosophies, advantages, disadvantages, and current market adoption in both domestic and global contexts.
The 18th China Linux Kernel Developer Conference (CLK 2023) will be held in Shenzhen on October 28, 2023, hosted by OPPO, and invites Linux kernel developers to submit technical papers (open call from September 22, deadline October 10) on topics such as architecture, scheduling, memory, storage, networking, virtualization, performance, testing and kernel use in IoT, mobile, automotive, cloud and AI, with required author bio, title and abstract.
This article provides a comprehensive technical review of Tesla's D1 AI processor and Dojo super‑computer architecture, covering its data‑flow near‑memory design, RISC‑V‑like instruction set, matrix compute units, chiplet packaging, power‑management, cooling solutions, and the associated software compilation ecosystem.
The 2023 semiconductor industry report forecasts ten key trends, including the dominance of mature process expansion, intensified policy environments, the rise of chiplet technology, FD‑SOI advancements, RISC‑V CPU IP breakthroughs, anti‑globalization shifts, front‑end integration by device makers, smart cockpit evolution, inventory cycle dynamics, and the push toward a fully domestic semiconductor ecosystem.
Go 1.20 RC1 introduces experimental RISC‑V/FreeBSD support, expands slice‑to‑array conversion, adds three new unsafe package functions, updates comparable type constraints, and changes struct value comparison order, while being the final version compatible with macOS 10.13/10.14, with download details provided.
This article provides a detailed introduction to System-on-Chip (SoC) technology, covering its definition, component hierarchy, IP‑core concepts, historical milestones, typical architectures, instruction‑set families, AI‑enabled variants, and current market dynamics across mobile, server, and high‑performance computing domains.
The article provides a comprehensive analysis of the 2022 CPU industry chain, market size, global landscape, and major vendors, covering the dominance of x86, the rise of ARM, Intel and AMD market dynamics, UMA attempts, and emerging architectures such as RISC‑V and Apple’s M1.
This report examines the rapid development, challenges, and future prospects of China's domestic CPU industry, covering market growth, technological breakthroughs, ecosystem building, and strategic considerations for manufacturers and policymakers in the global context.
This article provides a comprehensive overview of RISC‑V, covering its open‑source ISA philosophy, historical development, RISC versus CISC design trade‑offs, modular extensions, basic integer instruction set, register file, common extensions such as M, F, D, C, and examples of commercial implementations, illustrating why RISC‑V has become a leading architecture for modern processors.
MIPS Tech has shifted from its legacy CPU architecture to RISC‑V, unveiling the high‑performance, scalable eVocore P8700 and power‑efficient I8500 multi‑processor IP cores aimed at high‑performance, real‑time applications such as networking, data centers, automotive, and edge computing.
The article explains how RISC‑V’s open, customizable ISA, the shift toward free and unrestricted hardware design, and market pressures such as Moore’s law slowdown and AI‑driven compute demand together fuel its rapid adoption, ecosystem growth, and competitive edge over proprietary architectures.
This article reviews the historical evolution of computer architecture, analyzes the end of Dennard scaling and Moore's Law, discusses domain‑specific architectures, open ISAs like RISC‑V, security vulnerabilities, and emerging opportunities such as agile hardware development and specialized accelerators.
This article reviews the evolution of computer architecture, discusses the end of Dennard scaling and Moore’s law, highlights the rise of domain‑specific and RISC‑V designs, examines security challenges, and outlines future opportunities for more efficient, open, and agile hardware solutions.
The article outlines Wave Computing’s 2018 decision to open the MIPS Release 6 instruction set, describes the evolution and product lines of MIPS, compares the open‑source licensing and ecosystem of MIPS with RISC‑V, and discusses market adoption, commercial models, and future challenges.
This article clarifies common misunderstandings about RISC‑V and open‑source processors by explaining the distinction between instruction set specifications and implementations, the openness of the ISA, commercial versus open‑source micro‑architectures, and the geopolitical aspects of RISC‑V adoption.