MIPS Open Instruction Set (Release 6) Initiative and Comparison with RISC‑V

In December 2018 Wave Computing announced that it would open the MIPS instruction set architecture to semiconductor companies, developers and universities, as part of its “All‑in‑AI” strategy after acquiring MIPS in June 2018.

The MIPS ISA, first released in 1985, has evolved over more than 30 years; the latest public version is MIPS Release 6 (2014), which introduced new SIMD, DSP, multithreading and virtualization extensions, and after 2014 the architecture saw rapid development.

Release 6 differs from earlier releases by adding new instructions, removing rarely used ones, and reorganising opcode space, making it almost a new ISA while maintaining backward compatibility for earlier versions.

Wave’s Warrior product line implements the Release 6 core across three performance classes (M‑Class, I‑Class, P‑Class) and groups earlier cores into the Classic series; these IP cores target AI, automotive, consumer electronics, IoT and networking markets.

The MIPS open‑source plan only covers the Release 6 ISA and related extensions (SIMD, DSP, multithreading, microMIPS, virtualization, MCU); it does not include earlier releases, and licensees may implement the ISA without releasing source code.

Compared with the fully open RISC‑V ISA (BSD‑licensed), the MIPS open plan retains commercial licensing restrictions, leading to fewer products adopting Release 6; most traditional MIPS markets have shifted to ARM, and no second‑source chip implementing Release 6 is known.

The article also presents a comparison of processor‑level business models (open, IP‑licensed, proprietary) across ISA, IP core and SoC design layers, illustrating the limited open‑source SoC implementations for MIPS.

Overall, the MIPS open initiative provides some commercial advantages but faces challenges in ecosystem growth, licensing uncertainty, and competition from more open architectures such as RISC‑V.