BestHub
Sign in
Tag

processor

0 views collected around this technical thread.

IT Services Circle
IT Services Circle
Nov 30, 2023 · Fundamentals

China's Loongson 3A6000 CPU Reaches Intel‑Level Performance with Independent LoongArch Architecture

The newly released Loongson 3A6000 processor, built on the domestically designed LoongArch instruction set, delivers performance comparable to Intel's 10th‑gen i3‑10100F, features four high‑performance cores, advanced vector extensions, DDR4‑3200 memory support, and a secure trusted module, marking a major milestone for China's independent CPU development.

ChinaHardwareLoongson
0 likes · 7 min read
China's Loongson 3A6000 CPU Reaches Intel‑Level Performance with Independent LoongArch Architecture
Architects' Tech Alliance
Architects' Tech Alliance
Sep 24, 2023 · Fundamentals

Analysis of Major Domestic Server CPU Vendors in China (2022)

The article provides a comprehensive overview of China's six leading domestic server CPU manufacturers—Zhaoxin, HaiGuang, FeiTeng, KunPeng, Loongson, and ShenWei—examining their instruction‑set licensing models, product line‑ups, performance benchmarks, ecosystem maturity, and market prospects within the context of the country's digital‑economy and trust‑worthy computing initiatives.

ChinaDomesticServer
0 likes · 18 min read
Analysis of Major Domestic Server CPU Vendors in China (2022)
Architects' Tech Alliance
Architects' Tech Alliance
May 2, 2023 · Fundamentals

Overview of Huawei Kunpeng 920 Processor Architecture and Subsystems

The article provides a detailed technical overview of Huawei's Kunpeng 920 processor, describing its ARM‑based RISC architecture, chip organization, core and cluster hierarchy, security features, and the various compute, I/O, interrupt, network, SAS, and PCIe subsystems integrated on the SoC.

KunpengRISCSOC
0 likes · 11 min read
Overview of Huawei Kunpeng 920 Processor Architecture and Subsystems
Ops Development Stories
Ops Development Stories
Jul 13, 2021 · Fundamentals

Understanding Multi-Core Processor Architectures: SMP, UMA, NUMA & Cache Hierarchies

This article outlines the main server hardware architectures—SMP, UMA, and NUMA—explains shared-storage models, details multi-core cache structures from private L1 to shared L3, compares access latencies, and discusses inter-core communication mechanisms and cache coherency protocols.

NUMASMParchitecture
0 likes · 14 min read
Understanding Multi-Core Processor Architectures: SMP, UMA, NUMA & Cache Hierarchies
Architects' Tech Alliance
Architects' Tech Alliance
Apr 2, 2021 · Fundamentals

MIPS Open Instruction Set (Release 6) Initiative and Comparison with RISC‑V

The article outlines Wave Computing’s 2018 decision to open the MIPS Release 6 instruction set, describes the evolution and product lines of MIPS, compares the open‑source licensing and ecosystem of MIPS with RISC‑V, and discusses market adoption, commercial models, and future challenges.

Instruction Set ArchitectureMIPSOpen ISA
0 likes · 9 min read
MIPS Open Instruction Set (Release 6) Initiative and Comparison with RISC‑V
DataFunTalk
DataFunTalk
Nov 24, 2018 · Artificial Intelligence

Comprehensive Guide to Fine‑Tuning BERT on Chinese Datasets

This article provides a step‑by‑step guide for fine‑tuning Google’s open‑source BERT on Chinese datasets, covering model download, processor customization, code examples, training commands, and insights into the underlying TensorFlow estimator architecture and deployment considerations.

BERTChinese NLPFine-tuning
0 likes · 11 min read
Comprehensive Guide to Fine‑Tuning BERT on Chinese Datasets