MIPS Announces RISC‑V Based eVocore P8700 and I8500 Multi‑Processor IP Cores

MIPS Tech has announced that it is no longer focusing on its traditional MIPS CPU instruction set architecture and is now adopting a RISC‑V‑based design. The company introduced two new multi‑processor IP cores, the eVocore P8700 and I8500, promising "first‑class performance and scalability".

The eVocore P8700 is described as delivering "superscalar performance" and can scale up to 64 clusters, 512 cores, and 1,024 harts/threads, with a planned market release in the fourth quarter of the year. The I8500 targets efficiency, positioning itself as the most power‑efficient solution for SoC applications.

According to MIPS, these are its first products built on the open RISC‑V ISA standard. The eVocore family is intended to strengthen MIPS's position in high‑performance, real‑time computing markets such as networking, data centers, and automotive. Industry research predicts a 73.6% compound annual growth rate for RISC‑V‑based SoCs from 2020 to 2027, with the automotive sector alone expected to grow at 69.9%.

Analysts from Semico Research highlighted the continued adoption of RISC‑V in automotive and other sectors due to the advantages of an open software development environment. MIPS CEO Desi Banatao emphasized that the shift to RISC‑V aligns with the company’s goal to target the high‑performance segment of the processor market.

The eVocore IP cores feature extensive configurability, supporting up to 64 clusters, hardware virtualization, user‑defined extensions, multithreading, mixed debugging, and functional safety. They are designed for heterogeneous computing, allowing integration with accelerators and providing a coherence manager for system‑wide cache consistency.

These announcements were sourced from a semiconductor industry report and include references to additional technical resources and downloadable documents related to ARM architecture, RISC‑V, and other processor technologies.