Understanding RISC‑V and Open‑Source Processors: Clarifying Misconceptions and Architectural Basics

1. Introduction

Recently, several online articles have misinterpreted RISC‑V and open‑source processors, leading to confusion. This article explains the concepts of instruction set architecture (ISA), micro‑architecture implementation, open‑source models, and their relationship to RISC‑V.

ISA specifications and processor implementations are different layers; the ISA is a written standard, while the implementation is source code that realizes the ISA. RISC‑V is an ISA specification.

Based on x86, ARM, or RISC‑V ISAs, designers can create micro‑architectures and eventually fabricate chips. The intellectual property of the ISA and the implementation are independent.

"RISC‑V is open‑source" means the ISA is open, free, and publicly available, which differs fundamentally from x86 or ARM, but it does not imply that every processor implementation is open‑source.

Using the RISC‑V ISA, both open‑source community projects (e.g., Berkeley’s Rocket core) and commercial companies (e.g., China’s Pingtouge Xuantie‑910, Chip‑Come N200, YouSi WeiHe WH‑32) can develop free or licensed processor implementations.

For more details, see the Open ISA and Open‑Source Chip Development Report .

2. Analysis of a Recent Misleading Article

The article titled "RISC‑V Chairman Reveals: RISC‑V Is Not an Open‑Source Processor" contains several inaccurate statements. Below are clarifications:

Question 1

Did Krste Asanović claim that "RISC‑V is not open‑source"?

Asanović actually said: (a) RISC‑V is an ISA, not a processor; (b) RISC‑V can be used for both open‑source and commercial processors.

The ISA itself remains open, free, and publicly available. Whether a specific implementation is open‑source or proprietary depends on the developer.

Question 2

Will future RISC‑V‑based processors require licensing fees?

The ISA is free; designers can create open‑source or commercial implementations. The RISC‑V Foundation only maintains the ISA specification and does not charge for micro‑architecture designs or chip production.

Question 3

Is RISC‑V subject to U.S. export controls?

The ISA, being an open standard, is not subject to export restrictions. However, chips manufactured by U.S. companies using RISC‑V may be controlled, while chips developed outside the U.S. (e.g., China’s Xuantie‑910) are not.

The RISC‑V Foundation moved its headquarters to Switzerland in November 2019, emphasizing its commitment to openness and global service.

3. What Is an Instruction Set and Its Role?

An ISA defines the interface between software and hardware. It is a documented standard (e.g., x86, ARM, RISC‑V) that guides processor and software design. The ISA can be likened to a screw‑nut specification that ensures compatibility across different manufacturers.

4. Relationship Between RISC‑V and Open‑Source Processors

A processor consists of three layers: ISA, micro‑architecture design, and the final product. The ISA is a specification; the micro‑architecture is the implementation (source code); the product is the fabricated chip.

Open‑source processors refer to the micro‑architecture code being publicly available.

Commercial models (licensed or closed) may use the open ISA but keep the implementation proprietary.

RISC‑V offers three implementation models: Open‑source (e.g., Berkeley Rocket, lowRISC, E203) – RTL source is released. Licensable (e.g., SiFive, Andes, Pingtouge) – IP is licensed, source not released. Closed (e.g., Google, NVIDIA) – IP and source remain internal. Thus, while the ISA is free and open, the micro‑architecture can be open, licensed, or closed. 5. Why Develop Open‑Source Processors? Open‑source processor projects lower development cost and time, allowing teams to focus on incremental innovation. They accelerate iteration cycles and leverage the RISC‑V software ecosystem, strengthening domestic RISC‑V ecosystems and enhancing global competitiveness.