Overview of LoongArch: Loongson’s Independent Instruction Set Architecture

On April 15, Loongson announced via its official WeChat that the foundational architecture of its self‑defined LoongArch instruction set has passed evaluation by a well‑known domestic intellectual‑property assessment agency and was officially released at the 2021 Information Technology Application Innovation Forum.

LoongArch, first implemented in the 3A5000 processor, marks Loongson’s complete separation from MIPS. The architecture aims for advancedness, extensibility, and compatibility, integrating key features from X86, ARM, MIPS, and RISC‑V, and introduces special EFLAG‑producing instructions to accelerate flag simulations.

LoongArch defines 337 base instructions, 10 virtual‑machine extensions, 176 binary‑translation extensions, 1,024 128‑bit vector extensions, and 1,018 256‑bit vector extensions, totaling 2,565 native instructions. Its instruction format is a superset of MIPS, retaining RISC characteristics while expanding the number of formats from 3 to 10, increasing immediate field sizes and branch offsets, and simplifying addressing.

The architecture maintains a classic RISC layout with 32‑bit fixed‑length instructions, 32 general‑purpose registers, and 32 floating‑point/vector registers, removing delay slots and allowing PC‑relative jumps with larger offsets. Loongson also provides a LoongArch‑based Linux OS that can run native programs and, through binary translation, execute binaries compiled for MIPS, x86, ARM, and RISC‑V.

Binary translation on LoongArch follows a common workflow; because many LoongArch base instructions resemble MIPS, translation overhead is minimal, and translation efficiency for ARM and RISC‑V surpasses that for x86. Loongson plans to release a compiler that can translate MIPS assembly to LoongArch binaries, enabling C/C++ code with embedded MIPS assembly to compile without modification.

Key recent achievements include the completion of three major IP core families (GS132, GS264, GS464), BIOS and compiler kernel adaptations enabling SPEC CPU workloads on FPGA, ongoing OS compilation, and migration of Java, JavaScript, and .NET runtimes. The binary translation system LAT is near completion, with user‑mode translation for MIPS and x86 already functional.

A third‑party authority has performed intellectual‑property analysis of LoongArch, finishing domestic assessment by the end of 2020 and international assessment in 2021. Loongson intends to open LoongArch for free, offering IP cores comparable to Cortex‑A53‑class processors under a non‑litigation alliance, and plans to promote a lightweight LoongArch system for academic use.

The overall goal is to preserve legacy MIPS ecosystems while building an independent Chinese CPU ecosystem, reducing reliance on foreign instruction‑set licenses and enhancing national and industry security.