3D Chip Stacking Technologies Transform Computing: AMD Zen 3, Graphcore Bow AI, and Intel Ponte Vecchio

High‑performance processor research shows that extending Moore's Law requires new directions, as transistor scaling slows and chips approach size limits.

Recent years have seen system‑on‑chip developers break large designs into smaller chips and connect them within a single package, often using 2.5D interposers for dense interconnects.

To store more data on a single chip, designers must stack chips, creating thousands of connections per square millimeter and demanding innovations to manage heat and reliability.

IEEE Spectrum senior editor Samuel K. Moore highlighted three ways 3D chip technology is disrupting computing, focusing on AMD, Graphcore, and Intel.

AMD Zen 3 – Leveraging 3D stacking, AMD’s next‑gen CPU adds a small chip that provides additional memory, improving average performance by 19% even without extra cache. The Zen 3 architecture uses through‑silicon vias (TSV) to vertically stack a 64 MiB SRAM chip within the L3 cache, achieving dense 9 µm connections and improved thermal stability.

Graphcore Bow AI Processor – By adding a power‑delivery silicon chip to its AI accelerator, Graphcore boosts clock speed from 1.35 GHz to 1.85 GHz, reduces voltage, and improves neural‑network training speed by 40% while cutting power consumption 16% without software changes. The power‑delivery die uses stacked capacitors and TSVs for efficient low‑voltage operation.

Intel Ponte Vecchio – Designed for the Aurora exaflop supercomputer, Ponte Vecchio integrates 47 silicon dies containing over 100 billion transistors, using both 2.5D Co‑EMIB and 3D Foveros stacking. The base tile connects compute, cache, and I/O tiles via high‑density interconnects, employing TSVs and novel coaxial magnetic inductors to manage power, clocking, and thermal challenges.

These advances illustrate how 3D stacking, TSVs, and innovative packaging are essential for continuing performance growth in high‑performance and AI computing.