How Huawei’s Kunpeng 960 Uses the τ Law and 3‑D Stacking to Defy Moore’s Law

Amid global semiconductor bottlenecks, Huawei’s Kunpeng line shifts from 2‑D planar CPUs to 3‑D stacked architectures, with the 950 introducing a two‑layer design and the upcoming 960 promising a three‑layer stack, 4 GHz clocks and a 54% performance boost, illustrating the τ scaling theory and a new supernode strategy that could reshape domestic and global server markets.

3D stackingCPU architectureHuawei

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How Huawei’s Kunpeng 960 Uses the τ Law and 3‑D Stacking to Defy Moore’s Law

AI Frontier Lectures

Jan 12, 2026 · Industry Insights

Why LLM Inference Hits a Memory Wall – Four Hardware Research Directions

The article analyses the challenges of large‑language‑model inference, highlighting memory bandwidth and interconnect as the primary bottlenecks, and presents four research opportunities—high‑bandwidth flash, processing‑near‑memory, 3D memory‑logic stacking, and low‑latency interconnect—while evaluating current Nvidia solutions and proposing integrated architectural approaches.

3D stackingAI hardware researchLLM inference

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Why LLM Inference Hits a Memory Wall – Four Hardware Research Directions

Architects' Tech Alliance

May 2, 2022 · Fundamentals

3D Chip Stacking Technologies Transform Computing: AMD Zen 3, Graphcore Bow AI, and Intel Ponte Vecchio

The article explains how 3D chip stacking—illustrated by AMD's Zen 3 3D V‑Cache, Graphcore's Bow AI accelerator, and Intel's Ponte Vecchio—overcomes physical limits of transistor scaling, boosts performance, and reshapes high‑performance and AI computing architectures.

3D stackingAI acceleratorCPU architecture

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3D Chip Stacking Technologies Transform Computing: AMD Zen 3, Graphcore Bow AI, and Intel Ponte Vecchio

21CTO

Dec 9, 2021 · Artificial Intelligence

How Alibaba’s DAMO Academy Is Redefining AI with the First 3D‑Stacked Compute‑Memory Chip

On December 3, Alibaba’s DAMO Academy announced its first AI chip that integrates memory and compute using hybrid‑bond 3D stacking, promising ten‑fold performance gains and 300× energy efficiency for AI workloads such as recommendation systems, and marking a shift from traditional von Neumann designs.

3D stackingAI ChipCompute-in-Memory

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How Alibaba’s DAMO Academy Is Redefining AI with the First 3D‑Stacked Compute‑Memory Chip

Architects' Tech Alliance

Dec 13, 2018 · Fundamentals

Intel Unveils Sunny Cove 10 nm CPU Architecture and Foveros 3D Stacking Technology at Architecture Day 2018

At Intel Architecture Day 2018 the company announced its next‑generation Sunny Cove micro‑architecture built on 10 nm, detailed its roadmap through 2021, introduced the 3D‑stacking Foveros technology, previewed new integrated and discrete GPUs, and launched a deep‑learning reference stack for AI developers.

10nm3D stackingFoveros

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Intel Unveils Sunny Cove 10 nm CPU Architecture and Foveros 3D Stacking Technology at Architecture Day 2018

How Huawei’s Kunpeng 960 Uses the τ Law and 3‑D Stacking to Defy Moore’s Law

Why LLM Inference Hits a Memory Wall – Four Hardware Research Directions

3D Chip Stacking Technologies Transform Computing: AMD Zen 3, Graphcore Bow AI, and Intel Ponte Vecchio

How Alibaba’s DAMO Academy Is Redefining AI with the First 3D‑Stacked Compute‑Memory Chip

Intel Unveils Sunny Cove 10 nm CPU Architecture and Foveros 3D Stacking Technology at Architecture Day 2018

3D Chip Stacking Technologies Transform Computing: AMD Zen 3, Graphcore Bow AI, and Intel Ponte Vecchio

Intel Unveils Sunny Cove 10 nm CPU Architecture and Foveros 3D Stacking Technology at Architecture Day 2018