Overview of ARMv8 Architecture and the Transition from 32‑bit to 64‑bit

ARMv8 architecture supports both 32‑bit (AArch32) and 64‑bit (AArch64) execution states, introducing 64‑bit wide registers while maintaining backward compatibility with ARMv7 software.

In GNU/Linux documentation (except Red Hat and Fedora) AArch64 is often referred to as ARM64.

The Cortex‑A series now includes implementations for both ARMv8‑A and ARMv7‑A:

Cortex‑A5, A7, A8, A9, A15, and A17 are based on the ARMv7‑A architecture.

Cortex‑A53, A57, and A73 are based on the ARMv8‑A architecture.

ARMv8 processors can run software compiled for ARMv7‑A when operating in AArch32 mode; 32‑bit code runs on ARMv8 only when the processor is in AArch32 state.

The 64‑bit instruction set (A64) cannot run on ARMv7 processors.

The Changes from 32‑bit to 64‑bit

Moving to 64‑bit brings several performance improvements:

1. Larger register pool

A64 provides 31 general‑purpose 64‑bit registers, allowing up to eight function arguments to be passed in registers instead of the stack, which reduces overhead.

2. Wider integer registers

Wider registers enable more efficient execution of 64‑bit arithmetic, often completing in a single operation where 32‑bit processors would need multiple steps.

3. Larger virtual address space

64‑bit operation expands the virtual address space beyond the 4 GB limit of 32‑bit systems, enabling memory‑mapped large files and reducing OS‑reserved address constraints.

4. Larger physical address space

64‑bit pointers (8 bytes) allow access to more than 4 GB of physical memory, though they increase memory usage and may affect cache‑hit rates.

64‑bit pointers: 8 bytes

32‑bit pointers: 4 bytes

ARMv8‑A Architecture History

Earlier ARM versions (v4, v4T, v5TE, v6, v7‑A) were 32‑bit only. ARMv8‑A adds a 64‑bit execution state while keeping 32‑bit compatibility.

ARMv8‑A Features

Larger physical address space (supports > 4 GB RAM)

64‑bit virtual addressing

Automatic event signaling for efficient spin‑locks

Expanded register file (31 × 64‑bit registers)

Efficient 64‑bit immediate generation

Wider PC‑relative addressing (±4 GB)

16 KB and 64 KB translation granules to reduce TLB misses

New exception model simplifying OS and hypervisor design

Improved cache management with zero‑instruction cache clean

Hardware‑accelerated cryptography (3‑10× speed‑up)

Load‑Acquire/Store‑Release instructions for C++11, C11, Java memory models

NEON double‑precision SIMD for scientific and HPC workloads

ARMv8‑A Processors: Cortex‑A53, Cortex‑A57, Cortex‑A73

Cortex‑A53

A mid‑range, low‑power core with 1‑4 cores per cluster, supporting both 32‑bit and 64‑bit code, optional GICv3/4, and an optional L2 cache controller. It offers an 8‑stage pipeline, power‑gating, dual‑issue capability, and an optimized L2 cache.

Cortex‑A57

A high‑performance core aimed at mobile, tablet, and server markets, supporting up to four cores per cluster, AMBA5 CHI/ACE interconnects, and advanced power‑saving features. It includes a deep pipeline, way prediction, and enhanced L2 cache design.

Cortex‑A73

Introduced in 2016, the A73 implements the full ARMv8‑A profile with a 128‑bit AMBA 4 ACE interface, built on a 10 nm process, delivering ~30 % higher sustained performance than the A72.

References

[1]

ARMv8 development reference documentation:

https://developer.arm.com/documentation/#cf[navigationhierarchiesproducts]=Architectures,CPU%20Architecture,A-Profile,Armv8-A

[2]

IEEE 754‑2008 – Standard for Floating‑Point Arithmetic:

https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4610935

[3]

IEEE 1003.1‑2016 – POSIX Base Specifications, Issue 7:

https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7582338

[4]

IEEE 1149.1‑2001 – Test Access Port and Boundary Scan Architecture:

https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=938734

[5]

ARM Architecture Reference Manual – ARMv8‑A (DDI0487):

https://documentation-service.arm.com/static/623b2de33b9f553dde8fd3b0?token=

[6]

ARM Cortex‑A Series Programmer’s Guide for ARMv7‑A (DEN 0013):

https://developer.arm.com/documentation/den0013/latest/

[7]

ARM NEON Programmer’s Guide (DEN 0018):

https://developer.arm.com/documentation/den0018/a/

[8]

ARM Cortex‑A53 MPCore Processor Technical Reference Manual (DDI 0500):

https://developer.arm.com/documentation/ddi0500/e/BABJBFEJ

[9]

ARM Cortex‑A57 MPCore Processor Technical Reference Manual (DDI 0488):

https://developer.arm.com/documentation/ddi0488/h/

[10]

ARM Cortex‑A73 MPCore Processor Technical Reference Manual:

https://developer.arm.com/documentation/100048/0100/?lang=en

[11]

ARM Generic Interrupt Controller Architecture Specification (ARM IHI 0048):

https://developer.arm.com/documentation/ihi0048/b/

[12]

ARM Compiler armasm Reference Guide v6.01 (DUI 0802):

https://developer.arm.com/documentation/dui0802/b/

[13]

ARM Compiler Software Development Guide v5.05 (DUI 0471):

https://developer.arm.com/documentation/dui0471/latest

[14]

ARM C Language Extensions (IHI 0053):

https://developer.arm.com/documentation/ihi0053/d/

[15]

ELF for the ARM Architecture (ARM IHI 0044):

https://www.simplemachines.it/doc/aaelf.pdf