When Moore’s Law Hits the Wall, China Takes a New Chip Road with Huawei’s “Tau Law”

1. End of an Era

On May 25, 2026 in Shanghai, Huawei’s semiconductor president He Tingbo announced at ISCAS 2026 that the era of geometric scaling is ending. He cited the >$20 billion cost of TSMC’s 3 nm fab, €150 million per ASML EUV machine, and quantum tunneling leakage below 2 nm as evidence that Moore’s law has hit a physical ceiling, especially for China which lacks EUV.

2. The “Tau Law” – Time Scaling Instead of Geometric Scaling

He introduced the “Tau Law” (τ law), whose core idea is to replace “geometric scaling” with “time scaling”. Instead of shrinking transistors further, the focus shifts to reducing signal propagation delay across the entire chip‑to‑system stack. τ represents the time constant of signal switching in circuits.

He claimed that in the past six years Huawei has designed and mass‑produced 381 chips based on this principle.

3. Four Technical Pillars – A Multi‑Layer Co‑Optimization System

Device Layer – Reducing Physical Constants

Optimizing transistor and interconnect resistance and parasitic capacitance to minimize device‑level time constants.

Circuit Layer – Logic Folding

Traditional chips use a 2‑D layout causing long signal paths. Logic Folding stacks circuits three‑dimensionally, shortening critical paths. Reported results include a doubling of transistor density, 40 % performance gain and 30 % power reduction, all without EUV.

He announced that the upcoming “New Kirin” mobile chip, slated for autumn 2026, will fully adopt Logic Folding with a hybrid‑bond pitch of 1.5 µm.

Chip Layer – Software‑Architecture‑Chip Co‑Design

Instead of adding software after silicon, the design aligns software requirements with chip architecture from the start, controlling instruction and data flow at fine granularity to maximise parallelism.

System Layer – Lingqu Bus

Huawei’s self‑developed Lingqu bus redefines inter‑chip communication, delivering 15× bandwidth, reducing latency from 2 µs to 200 ns, and supporting up to 8192 cards, enabling mature‑process clusters to train large AI models.

4. Roadmap to 2031 – 1.4 nm Equivalent Density Without EUV

Autumn 2026 : New Kirin with Logic Folding enters commercial use.

2031 : High‑end chips based on the Tau Law achieve performance equivalent to a 1.4 nm process, even though they run on 7 nm/14 nm nodes.

The term “equivalent level” emphasises performance parity rather than identical lithography.

5. Western Reaction

Bloomberg headlined that Huawei claims a chip breakthrough that narrows the gap with TSMC, while Reuters noted the announcement comes amid U.S. sanctions. Both outlets reported the factual basis of 381 mass‑produced chips.

He concluded with “the future belongs to open collaboration,” signalling that the Tau Law’s impact depends on global ecosystem participation.

6. Conclusion

The Tau Law does not overturn Moore’s law; it offers a new “track” by optimising time rather than size, providing a viable path for China’s semiconductor industry when advanced nodes are inaccessible.