How Huawei’s “τ Law” Redefines Chip Scaling by Shrinking Time, Not Geometry

At ISCAS 2026, Huawei’s He Tingbo unveiled the “τ Law,” a time‑scaling theory that replaces geometric miniaturization with LogicFolding to cut signal‑travel time, delivering up to 55% higher transistor density, 41% better SoC efficiency, and a portfolio of 381 chips over six years.

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ZhiKe AI
How Huawei’s “τ Law” Redefines Chip Scaling by Shrinking Time, Not Geometry

τ Law definition

τ Law proposes replacing geometric scaling of transistors with time‑scaling, i.e., systematically reducing the circuit time constant τ to shorten internal signal propagation.

LogicFolding technique

LogicFolding stacks circuit layers vertically, converting planar routing into a multi‑story structure where inter‑layer connections act as “elevators”. This reduces signal travel distance by orders of magnitude compared with conventional planar layouts.

Experimental results

Transistor density increase of 55 % per generation.

SoC energy‑efficiency improvement of 41 %.

SRAM frequency increase of 40 %.

First production chip (autumn 2026) reports 40 % CPU/GPU performance uplift, 35 % efficiency gain, and effective density comparable to a 3 nm process.

Development timeline

2004 – HiSilicon founded, He Tingbo appointed lead.

2017 – Kirin 970 first SoC with integrated NPU.

2018 – Kirin 980 first 7 nm mobile SoC.

May 2019 – U.S. entity‑list restriction blocks access to TSMC advanced nodes.

2020‑2023 – Kirin chips withdrawn, HiSilicon revenue fell ~70 %.

Aug 2023 – Mate 60 Pro released, Kirin re‑introduced.

2025 – Kirin 9030 mass‑produced, based on self‑developed Tai‑Shan architecture.

May 25 2026 – ISCAS 2026 presentation of τ Law.

Significance

Physical limit: transistor thickness approaching a few dozen atoms leads to leakage, heat, and loss of control. Economic limit: a 3 nm fab costs >$20 billion for modest performance gains. τ Law shifts scaling from space to time, providing a path that does not depend on external advanced‑process access.

Scale of effort

From 2020 to 2026 the team designed and fabricated 381 distinct chips covering smartphones, AI accelerators, servers, and automotive electronics, serving over 1 billion users.

References

He Tingbo, “A Time Scaling Theory for Multi‑Layer Electronic Systems”, Chinese Academy of Sciences pre‑print platform, 2026‑05‑25.

ISCAS 2026 keynote, 2026‑05‑25.

Huawei annual reports and official announcements, 2025‑2026.

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chip designsemiconductorHuaweilogic foldingtime scalingISCAS2026
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