This article compares the major instruction set architectures—x86, ARM, and RISC‑V—explaining their CISC versus RISC philosophies, historical evolution, technical trade‑offs, and the current market landscape of domestic and global CPU vendors.
At Computex 2024, AMD showcased its latest CPU, GPU, and AI‑accelerated technologies—including the high‑performance Zen 5 core, second‑generation XDNA NPU with 50 TOPS, the Ryzen 9000 consumer processor, the AI‑PC Strix Point platform, Versal AI Edge Gen 2, the upcoming MI‑series AI GPUs, and the new UA‑Link interconnect—highlighting the company’s roadmap for next‑generation computing and AI workloads.
This guide explains why MySQL or Java processes can consume 700‑900% CPU in production, walks through step‑by‑step diagnosis using Linux tools, and provides concrete remediation techniques such as indexing, caching, thread analysis, and code adjustments to restore normal performance.
The article analyzes the limits of the von Neumann model and Moore's law, explains how instruction set complexity defines processor categories, and argues that integrating CPUs, GPUs, FPGAs, DPUs and ASICs into a super‑heterogeneous ecosystem—driven by Intel, NVIDIA, ARM and emerging trends—will shape the future of computing through diverse workloads, AI demand, green efficiency and a global compute network by 2030.
This comprehensive guide introduces the core concepts of server hardware, covering CPU architectures, memory, storage devices and RAID configurations, as well as network interface cards, their classifications, functions, and common standards, providing a solid foundation for understanding modern data center infrastructure.
This guide walks through real‑world scenarios of high CPU and memory alerts, demonstrating how to use Linux's top tool, interpret its detailed output, convert thread IDs, and leverage jstack dumps to pinpoint and resolve performance bottlenecks.
This article walks you through a systematic approach to identify the root cause of a Linux server's CPU hitting 100%, from pinpointing the high‑load process with top, tracing the responsible business code, to using a custom shell script that streamlines thread analysis and resolves the overload.
This article provides a complete Bash script that gathers Linux system metrics—including IP address, CPU core count, utilization percentages, load averages, memory and swap usage, and disk I/O statistics—while explaining each command (ifconfig, grep, awk, top, vmstat, free, iostat, uptime) and how the script assembles the results.
This article introduces x86 assembly language, explaining its historical origins, the role of CPU registers such as EAX and ESP, the heap and downward‑growing stack memory models, and demonstrates basic stack‑frame operations like push, call, mov, add, pop, and ret through a simple compiled example.
This article explains the fundamentals of CPUs, covering their definition, core functions, internal structure, registers, instruction cycles, assembly language, branching, and how they interact with memory and I/O devices to execute programs.
This article breaks down the official and tested PC hardware requirements for Black Myth: Wu Kong, covering CPU, GPU, RAM, and ray‑tracing needs across 1080p, 2K, and 4K resolutions, and offers practical build recommendations for each performance tier.
This article presents a practical guide for backend developers to troubleshoot Linux performance problems, covering essential analysis tools, a systematic diagnosis method, and detailed checklists for CPU, memory, disk I/O, and network I/O issues.
This guide walks you through identifying a CPU‑mining malware infection on a Linux server, from spotting abnormal CPU usage with top, tracing the malicious executable, disabling its cron job, and safely cleaning the infected files and processes.
This article outlines practical troubleshooting steps for eight frequent production problems—including OOM, CPU spikes, interface timeouts, index failures, deadlocks, disk issues, MQ backlogs, and API errors—providing clear guidance and code snippets to help engineers quickly identify root causes and resolve them.
The article presents a concise mind‑map of essential Linux performance tools and a flexible troubleshooting workflow, guiding backend developers through CPU, memory, disk, and network issues by using utilities such as top, oprofile, slabtop, iotop, netstat, and strace to quickly pinpoint and resolve bottlenecks.
This article explains the evolution of CPU cache, its underlying principles of temporal and spatial locality, various cache architectures, implementation details, and practical considerations such as cache line size and replacement policies, providing a comprehensive overview for developers and computer engineers.
From raw binary on punched tape to mnemonic assembly and then to high‑level constructs like if, while, and functions, programmers created recursive grammars that compile source code into abstract syntax trees, which a compiler translates back into machine instructions, illustrating how recursion underpins both programming language design and computation.
The Venado supercomputer, unveiled at Los Alamos, combines Nvidia Grace CPUs, Hopper GPUs, HPE Slingshot interconnects, and massive memory bandwidth to achieve a 15.6‑petaflop FP64 peak, illustrating the evolving balance between CPU and GPU workloads in modern high‑performance computing.
This article explains the role of the CPU, its internal structure, key components like the control unit and ALU, registers, program counter, and how instructions are fetched, decoded, executed, and written back, using clear diagrams and examples.
This article outlines the main directions for server performance tuning—CPU, memory, disk, and network—explains the typical workflow of metric collection, bottleneck analysis, and parameter optimization, and provides a curated list of recent CPU industry reports and technical resources.
The 2024 China server CPU industry overview analyzes the dominance of X86 and ARM ecosystems, presents market size growth from 2018 to 2028, examines competitive advantages of domestic vendors, and discusses policy-driven demand and pricing challenges shaping the domestic CPU market.
This guide maps Linux kernel subsystems to key performance metrics and presents a curated set of CPU, memory, disk I/O, and network tools—complete with visual charts, metric explanations, and practical notes for effective system analysis.
At Computex 2024 AMD showcased its latest Zen 5 CPU core, second‑generation XDNA NPU with 50 TOPS AI performance, the consumer‑grade Ryzen 9000 series, AI‑focused Strix Point processors, Versal AI Edge Gen 2, upcoming AI GPUs like MI325X/MI350/MI400, and the new UA‑Link 1.0 networking standard.
This article explains common scenarios that cause MySQL or Java processes to consume 900% CPU, walks through step‑by‑step diagnosis using Linux tools, and provides concrete optimization techniques such as indexing, caching, thread analysis, and code adjustments to bring CPU usage back to normal levels.
The article investigates undocumented x86 opcodes, describing a depth‑first search that uses page‑faults to locate hidden instruction boundaries, and reports finding dozens of executable but undocumented instructions on Intel and AMD CPUs, highlighting potential security risks and the need for vigilant hardware analysis.
This guide walks you through Linux's built‑in utilities—such as cat, free, vmstat, lsblk, ip, ethtool, top, htop, and Glances—to display and analyze CPU, memory, storage, and network information, helping you monitor system health and plan upgrades.
This article investigates two real‑world performance incidents—one caused by excessive disk I/O from a misconfigured Filebeat and another by kernel memory‑fragmentation bugs triggered by a trace feature—detailing observations, Linux diagnostic commands, analysis, and practical remediation steps.
By following Ben Eater’s step‑by‑step tutorial, a non‑computer‑science student assembled a fully functional 8‑bit CPU on a breadboard using a 555‑timer clock and TTL chips such as 74LS173 and 74LS245, spending two months on half‑hour daily sessions to achieve a working processor that deepened their grasp of computer architecture and basic electronics.
CPU efficiency depends on low CPI and high cache‑hit rates, which can be measured on Linux using the high‑level perf utility or the low‑level perf_event_open syscall to read hardware performance counters for cycles, instructions, and cache‑miss statistics, revealing how often the processor falls back to slower memory.
This article explains how CPUs interpret binary signals as voltage levels, describes basic logic gates such as AND, OR, NOT, shows how they combine to perform arithmetic like addition, and clarifies that hardware itself lacks understanding, relying on human-designed instruction sets and compilers to give meaning to 0s and 1s.
This article introduces Linux perf, explains how to install it, demonstrates basic commands such as perf‑list, perf‑stat, perf‑top, perf‑record and perf‑report, and shows how to combine perf with flame‑graphs to locate CPU‑bound hotspots and other performance bottlenecks in applications and the kernel.
This article explains why threads are essential for performance, how to create and configure Java thread pools using the Executors utility, distinguishes CPU, IO, and scheduled pool types, and demonstrates monitoring techniques for latency and deadlock detection with practical code examples.
The article explains that a CPU merely reacts to voltage signals without any comprehension, illustrating how binary 0/1, logic gates, and combinational circuits form the basis of computation, and why compilers—not the CPU—interpret programming languages before execution.
This article explains server CPU memory controller architecture, detailing the six DDR4 channels, the differences between UDIMM, RDIMM, LRDIMM, and SO‑DIMM modules, how bandwidth is calculated, and the role of ECC memory in ensuring data integrity for enterprise systems.
This article details the migration of the Cloud Music desktop client from a legacy NEJ‑CEF hybrid to a React‑based architecture, outlines four major performance challenges, and explains the step‑by‑step optimizations—including API preloading, render memoization, virtual‑list replacement, and resource‑usage reductions—that cut startup latency by 48%, eliminated interaction stutter, and dramatically lowered CPU, GPU, and memory consumption.
GaussDB provides a fine‑grained resource control solution that lets administrators define CPU, memory, I/O, connection, concurrency, and storage limits at user, session, and statement levels, using resource pools, control groups, and GUC parameters to ensure multi‑tenant isolation, SLA compliance, and optimal cluster utilization.
Linux’s “watchdog: BUG: soft lockup – CPU#1 stuck” warning indicates a CPU soft lockup, caused by driver bugs, hardware faults, or kernel issues, and can be resolved by updating software, monitoring hardware, analyzing logs, and implementing preventive performance and hardware checks.
Since 2023 users have reported that Intel's flagship desktop CPUs i9-13900K and i9-14900K suffer stability problems, especially during gaming, which Intel attributes to non‑standard BIOS configurations on 600/700 series motherboards that disable critical thermal and power protections.
This article explains the basic functions of CPUs and GPUs, their advanced capabilities and real‑world applications, and compares their architectures, processing models, and roles in environments such as IoT, mobile devices, Kubernetes, and AI workloads.
This article compiles seven hands‑on Linux performance‑optimization practices—including hardware, kernel, and network tuning, diagnostic commands, memory accounting, swap usage, and TCP parameter adjustments—to help engineers quickly identify and resolve stability and speed issues in production environments.
This guide walks you through checking CPU usage, system load, resource consumption, problematic processes, system logs, and performance bottlenecks on a Linux server using common command‑line tools such as top, uptime, pidstat, strace, tail, and perf.
The talk outlines how modern data centers host diverse CPUs (Intel, AMD, Ampere, ARM), the multi‑layer performance‑tuning challenges this creates, and how Baidu Cloud’s one‑click Btune suite automates metric collection, bottleneck identification, and optimization across hardware, kernel, runtime, and application layers.
This article explains the architecture of server‑grade CPU memory controllers, covering memory channel counts, bandwidth calculations, the differences between UDIMM, RDIMM and LRDIMM modules, and the role of ECC in ensuring data integrity.
This guide introduces the Linux lscpu command, explains its syntax and common options, provides example outputs in default, parsable and extended formats, clarifies each field's meaning, and offers practical usage notes for accurate CPU information retrieval.
This article explains the fundamentals of a CPU, covering its definition, core functions, internal structure, registers, instruction cycle, assembly language basics, program counter, branching, flag registers, function calls, and how memory addressing enables array-like operations.
The article describes how the author followed Ben Eater’s step‑by‑step tutorial to hand‑assemble a functional 8‑bit CPU on a breadboard, detailing required components, sourcing parts in China, wiring procedures, and practical tips for beginners interested in computer architecture and electronics DIY.
This article explains common causes of extreme CPU usage in MySQL and Java applications, provides step‑by‑step troubleshooting methods using Linux tools and SQL commands, and presents real‑world case studies with concrete optimizations such as indexing, caching, and thread‑handling adjustments.
This guide walks through diagnosing excessive CPU load and memory consumption in Java applications, using tools like top, jstack, jmap, and jstat, and provides step‑by‑step solutions and JVM tuning parameters to reduce GC pauses and prevent full garbage collections.
This guide walks you through checking CPU utilization, system load, process resource consumption, tracing problematic processes, reviewing logs, and using performance tools to pinpoint and resolve high CPU usage on a Linux server.
Server CPUs differ from desktop CPUs in size, price, integrated graphics, core count, memory support, scalability, and clock frequency, featuring larger dies, higher cost, no graphics, many more cores, ECC memory with many DIMM slots, multi‑CPU linking, and lower, more stable clock speeds.
Typical reasons for Java backend services hitting 100 % CPU include fetching massive data sets, misusing Kafka auto‑acknowledge, infinite loops or recursion, thread‑pool overload causing context‑switch thrashing, bulk file synchronization, lock‑order deadlocks, poorly designed regular expressions, and intensive real‑time calculations under high concurrency.
This article examines common reasons behind persistent 100% CPU usage in Java backend systems—ranging from excessive full GC and Kafka auto‑acknowledgment to dead loops, thread‑pool overload, massive file sync, deadlocks, inefficient regex and heavy real‑time calculations—offering practical diagnostics and solutions.
This article explains the meaning of 32‑bit and 64‑bit labels for CPUs, operating systems, software and integer types, shows how source code becomes machine code and a running process, and clarifies the memory‑addressing limits and compatibility rules of each architecture.
CPU, the brain of a computer, is a tiny chip that fetches, decodes, and executes instructions, comprising control units, ALU, registers, and interacts with memory, while supporting programming concepts like assembly, conditionals, loops, and function calls, all illustrated with diagrams and examples.
This article analyzes typical reasons why Java backend services experience sustained 100% CPU usage—such as bulk data retrieval, Kafka auto‑acknowledgement, infinite loops, excessive multithreading, massive file synchronization, deadlocks, inefficient regular expressions, and heavy real‑time calculations—and offers practical mitigation strategies.
This article explains the key Linux performance indicators—CPU, memory, disk I/O, file system, and network—describes how to monitor them with commands like top, vmstat, iostat, iotop, and smem, and provides practical guidance on interpreting the results to identify and resolve system bottlenecks.
This article examines eight common reasons why Java backend services experience 100% CPU usage—such as fetching excessive data, automatic Kafka acknowledgments, infinite loops, multithreaded imports, massive file syncs, deadlocks, inefficient regular expressions, and heavy real‑time calculations—and provides practical mitigation strategies.
This guide walks through systematic troubleshooting of Java applications by checking CPU, disk, memory, and network layers, using tools like jstack, jmap, vmstat, iostat, and tcpdump to pinpoint and resolve performance and stability problems.
Server CPUs differ from desktop CPUs in size, price, integrated graphics, core count, memory support, scalability, and clock frequency, with server chips being larger, more expensive, lacking integrated graphics, offering more cores, ECC memory, multi‑CPU interconnects, and lower base frequencies for stability.
After migrating workloads to a new CPU platform, unexpected performance regressions can occur, but Baidu Cloud's Btune tool provides automated, multi‑dimensional analysis and actionable optimization suggestions that helped a test program improve its execution time by 36.8% through memory and NUMA tuning.
This article explains what a CPU is, how it processes instructions through fetch‑decode‑execute stages, its internal components such as the control unit, ALU and various registers, the role of memory and program counters, and introduces assembly language concepts and branching mechanisms.
The article examines how CPUs, GPUs, and memory have long formed the core of PC hardware, discusses the emerging role of NPUs for AI processing, and describes Intel's Lunar Lake strategy of integrating memory with the processor to deliver faster, lower‑latency performance in upcoming AI‑focused PCs.
Tech blogger Inkbox demonstrates how to construct a fully functional 16‑bit CPU, complete with 128 KB RAM, a 128×128 pixel display, and a custom 23‑instruction assembly language called Excel‑ASM16, all implemented purely within Microsoft Excel without any VBA scripts or plugins.
The article analyzes the global CPU and GPU markets, showing Intel and AMD's overwhelming share, the rise of new data‑center players, key performance metrics for CPUs, the constraints of instruction‑set ecosystems, and emerging AI‑chip design trends that could open space for domestic Chinese manufacturers.
The article examines Nvidia's GH200 superchip and AMD's Instinct MI300, compares CPU, GPU, FPGA, and ASIC architectures, analyzes market share trends, and discusses opportunities for domestic chip makers in the rapidly evolving AI compute landscape.
This article demystifies the CPU by defining its role as the computer's brain, describing the fetch‑decode‑execute cycle, detailing its internal components such as the control unit, ALU and various registers, and explaining how instruction sets, assembly language, program counters, flags, function calls, and array addressing work together to run programs.
This article provides a comprehensive, step‑by‑step overview of CPU fundamentals, covering its definition, core functions, internal architecture, key registers, instruction execution stages, program counter behavior, conditional branching, flag registers, function calls, memory addressing, and the classic fetch‑decode‑execute pipeline.
This article introduces the Xinchuang (information technology innovation) industry, outlines its hardware components, and provides concise explanations of CPU concepts, instruction sets, GPU architecture and operation, as well as storage classifications, while also linking to related research reports and promotional resources.
This guide walks you through checking CPU usage, system load, process resources, tracing problematic processes, reviewing system logs, and using performance tools like perf to pinpoint and resolve Linux server bottlenecks.
The Linux top command offers a dynamic, real‑time view of system processes and resource usage—showing overall statistics, CPU and memory breakdowns, and detailed process columns—while supporting customizable refresh intervals, batch mode, and interactive shortcuts for sorting, column selection, and monitoring crucial metrics like %idle, %wa, and %steal.
This guide explains how to use the Linux top command to monitor real‑time process changes, interpret system and process statistics, apply command‑line options, perform common interactive operations, and understand CPU steal time for virtualized environments.
The 2023 Xinchuang industry report outlines how China's information‑technology innovation sector entered a rapid growth phase, highlighting market expansion, dominant keywords, the evolving hardware ecosystem—including CPUs, GPUs, AI chips, DPU and cloud databases—and the strategic shift toward full‑industry adoption across eight critical sectors.
To cope with soaring traffic on Bilibili’s effect‑advertising engine, the team systematically measured latency, eliminated redundant Redis calls, switched JSON to Protobuf, applied branch‑prediction hints, loop‑unrolling and AVX256 SIMD, introduced object‑pooling and an inverted‑index request format, cutting CPU usage by 21 % and boosting peak throughput 13 %.
An in‑depth overview of AI server components, market growth, AIGC‑driven demand, heterogeneous computing architectures, major vendors, and future trends, highlighting hardware composition, cost breakdown, competitive rankings, and the impact of GPU, CPU, and emerging AI accelerators on the industry.
This article explains a three‑step method—using top to locate the CPU‑hungry Java process, identifying the offending thread, and printing its stack with jstack—to pinpoint and resolve excessive CPU consumption in a Java application running on Linux.
When a computer has no active user tasks, the CPU appears idle but actually runs a special system idle process that repeatedly executes the privileged halt instruction, allowing the processor to enter low‑power states while the operating system manages process queues and scheduling.
When a production container suddenly hit over 90% CPU and excessive JVM garbage collection, the author walks through entering the pod, using top and top‑H to locate the offending thread, extracting its stack with jstack, downloading the data via a simple HTTP server, and ultimately discovering an Excel export routine that caused massive object allocation, fixing the code and restoring stability.
The article provides a comprehensive overview of CPU architecture, covering the distinction between x86 and non‑x86 processors, packaging types, internal components such as the IHS, TIM, die and interposer, the execution pipeline of a Core i7, cache hierarchy, performance metrics, and common cache replacement algorithms.
The 2023 Chinese server CPU industry report details the sector’s rapid growth, classification by instruction set architectures, market characteristics, supply chain analysis, size fluctuations, future forecasts, and competitive dynamics among domestic and foreign manufacturers.
The newly released Loongson 3A6000 processor, built on the domestically designed LoongArch instruction set, delivers performance comparable to Intel's 10th‑gen i3‑10100F, features four high‑performance cores, advanced vector extensions, DDR4‑3200 memory support, and a secure trusted module, marking a major milestone for China's independent CPU development.
The article explains CPU overclocking, covering its feasibility, required high‑quality motherboard, memory and cooling, the relationship between external frequency, multiplier and core speed, and the potential hazards such as increased heat, system instability, reduced component lifespan, and voltage considerations.
The team traced read‑request timeouts to a single overloaded Elasticsearch node where an excessively high node_concurrent_recoveries setting caused many simultaneous shard recoveries and disk‑watermark‑driven relocations, and resolved the issue by lowering concurrent recoveries, enabling adaptive replica selection, and adjusting allocation settings.
The article outlines the major milestones in CPU development—including shrinking process nodes, increasing integration of components, evolving memory controller standards, the progression of PCIe generations, and micro‑architectural enhancements such as larger caches and hybrid core designs—providing a concise historical overview for readers.
This article walks through a real‑world investigation of a pod whose CPU spiked to over 90%, detailing how abnormal JVM garbage‑collection patterns were identified, traced to a specific Java thread, and resolved by fixing an inefficient Excel export routine.
This article explains the fundamental principles of computer operation, covering the von Neumann model, CPU and RAM interaction, instruction sets, memory hierarchy, caches, endianness, compilers, operating systems, and performance optimizations, while illustrating each concept with diagrams and code examples.
This article traces the evolution of CPUs by examining process node reductions, increasing integration of components, memory controller upgrades, PCIe advancements, and microarchitectural innovations that together shape modern processor performance and efficiency.
This article details how Didi identified excessive CPU consumption by ClickHouse's BgMoveProcPool threads, traced the root cause to unnecessary part‑move checks, introduced a simple early‑exit guard in selectPartsForMove, and achieved a dramatic reduction in CPU load while contributing the fix upstream.
This article provides a comprehensive overview of CPU fundamentals, covering core concepts such as clock speed, external frequency, front‑side bus, multiplier, bit and word length, cache hierarchy, instruction sets, voltage levels, manufacturing processes, pipelines, superscalar execution, SMP, multicore designs, multithreading, hyper‑threading, and NUMA technology.
A Java ToB system struggled to meet a 500 requests‑per‑second target, revealing hidden bottlenecks such as slow SQL, excessive logging, thread‑pool misconfiguration, high CPU usage from Spring bean creation, and improper Redis usage, which were systematically identified and mitigated.
This article explains the structure and evolution of modern CPUs, covering the core (die), substrate, filler material, packaging technologies, and the various interface types that connect the processor to the motherboard, while highlighting current trends such as integration of GPU cores and advanced manufacturing processes.
This article explains Intel's CPU naming conventions, generation identifiers, SKU and suffix meanings, details the evolution of Intel processor generations from Haswell to Raptor Lake Refresh, and examines the internal microarchitecture of a Kaby Lake i5‑7200U, including its die layout and core components.
This article explains Intel's CPU naming conventions, the meaning of each part of a processor model string, the evolution of CPU generations from Haswell to Raptor Lake Refresh, and the internal micro‑architecture of a Kaby Lake i5‑7200U, illustrated with die diagrams and code examples.
The article details a step‑by‑step investigation of a Java Spring backend that initially achieved only 50 req/s under load, identifies bottlenecks such as slow SQL, excessive logging, thread‑pool misconfiguration and costly Spring bean creation, and demonstrates how targeted optimizations roughly doubled throughput while reducing response times.
This article explains how CPU core count, clock speed, and cache, as well as GPU shader count, frequency, memory bandwidth, and graphics‑card memory size and interface affect performance, and shows 2023 desktop and laptop performance ladder charts to help users compare and choose the right hardware.
According to Reuters, Nvidia and AMD are designing Arm‑based processors for Windows PCs that could be ready by 2025, while Microsoft continues its partnership with Qualcomm on Arm Windows 11 and rumors suggest Microsoft may also develop its own Arm server chips.
This article explains the fundamental principles of how computers operate, covering the basic architecture of CPUs and memory, the role of buses and registers, instruction sets, compiler translation, cache hierarchies, storage layers, and the impact of 32‑bit versus 64‑bit designs.
This article provides a concise technical overview of server hardware, covering CPU architecture and platform options, GPU evolution and key specifications, and DDR4 memory compatibility rules, helping readers understand the essential components for building or upgrading a server.
High Bandwidth Memory (HBM), introduced in 2014 using TSV stacking, has evolved through HBM2, HBM2e, and HBM3 standards and is now integrated into CPUs, GPUs, and accelerators from AMD, NVIDIA, Intel, and others, with advanced interconnects like CoWoS, EMIB, and Foveros enabling high‑capacity, high‑bandwidth packaging.
The article provides a comprehensive overview of China's six leading domestic server CPU manufacturers—Zhaoxin, HaiGuang, FeiTeng, KunPeng, Loongson, and ShenWei—examining their instruction‑set licensing models, product line‑ups, performance benchmarks, ecosystem maturity, and market prospects within the context of the country's digital‑economy and trust‑worthy computing initiatives.
This article explains how a CPU fetches and executes instructions, how processes and threads are created and managed, and why thread pools are crucial for efficiently handling short‑lived tasks on modern multi‑core systems.
