Understanding Intel CPU Naming Rules, Generations, and Microarchitecture

On October 16, Intel officially launched its 14th‑generation Core processors, prompting the author to explain the often‑confusing CPU model specifications.

The article breaks down Intel's CPU naming scheme into five parts: brand mark, brand modifier, generation number, SKU, and product‑line suffix.

The brand mark identifies the manufacturer (Intel or AMD) and the sub‑brand such as Core, Celeron, Pentium, Xeon, or Atom, each targeting different market segments.

The brand modifier (i3, i5, i7, i9) indicates the performance tier within a generation, ranging from low‑end to high‑end.

The generation number (e.g., "7" in i5‑7200U) denotes the micro‑architecture era; a 7 indicates the 2016 Kaby Lake architecture, with higher numbers representing newer designs.

The SKU is an internal inventory identifier that generally, but not always, correlates with performance.

The suffix (U, H, Y, X, K, T, etc.) conveys power and performance characteristics, such as low‑power U‑series for laptops or high‑performance K‑series for desktops.

A reference table lists Intel CPU generations from the 4th‑generation Haswell (22 nm) up to the 14th‑generation Raptor Lake Refresh (7 nm), showing release year, code name, process node, and micro‑architecture.

The author uses a ThinkPad x270 with the CPU Intel(R) Core(TM) i5-7200U CPU @ 2.50GHz 2.71 GHz as a concrete example to illustrate the naming components.

This specific model is a Core brand, i5 tier, 7th‑generation Kaby Lake, SKU 200, and U‑suffix indicating low‑power usage.

Recent examples such as Intel(R) Core(TM) i9-14900K , Intel(R) Core(TM) i7-14700K , and Intel(R) Core(TM) i5-14600K show the continuation of the same naming pattern for the 14th generation.

The article then examines the die layout of the i5‑7200U, highlighting the integrated graphics (Gen9.5), two physical cores, shared L3 cache, and the memory controller that supports DDR4‑2400.

It describes the System Agent module, which includes PCIe lanes, the Image Processing Unit (IPU), and other peripheral interfaces.

The southbridge functions as the bridge between the CPU and I/O devices, aggregating data from storage, network, and other peripherals before passing it to the CPU.

The IPU provides hardware acceleration for video encoding, face detection, and other image‑processing tasks.

Finally, the micro‑architecture of the Kaby Lake core is dissected into three regions: the Front End (instruction fetch, decode, branch prediction, L1 instruction cache, and TLB), the Execution Engine (ports handling integer, floating‑point, address generation, load/store operations, capable of up to eight µ‑ops per cycle), and the Memory Subsystem (L1 and L2 data caches, L3 cache, and Data TLB).

The author concludes that understanding these naming rules and internal structures helps developers quickly assess a CPU's capabilities and encourages further exploration of performance benchmarks.