Understanding CPU Memory Controllers: Channels, Bandwidth, and DIMM Types (Skylake Server CPUs)

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In a previous article we explored the internal architecture of server CPUs and saw that they contain an integrated memory controller (IMC). This article dives deeper into the IMC parameters.

Below is a snippet showing the memory support of a Skylake‑generation server CPU:

DRAM
6 channels of DDR4, up to 2666 MT/s
RDIMM and LRDIMM
bandwidth of 21.33 GB/s
aggregated bandwidth of 128 GB/s

Key questions raised:

What does "6 channels" mean?

What are RDIMM and LRDIMM?

Why is the per‑channel bandwidth 21.33 GB/s while the aggregated bandwidth is 128 GB/s?

Memory Channels and Bandwidth

Skylake CPUs have two memory controllers, each with a DDR PHY that bridges the controller and DDR4 DIMMs. Each PHY provides three DDR4 channels, each channel supporting two DIMM slots, giving a total of six channels and up to twelve DIMMs.

The memory frequency is 2666 MT/s. With a 64‑bit (8‑byte) data path, the bandwidth per channel is 2666 M × 8 = 21.33 GB/s, and the total bandwidth across six channels is 21.33 GB/s × 6 ≈ 128 GB/s.

DIMM Module Types

DIMM (Dual In‑Line Memory Module) is the standard memory module today. Variants include:

UDIMM : Unbuffered DIMM, used mainly in desktops.

SO‑DIMM : Small‑Outline DIMM for laptops.

RDIMM : Registered DIMM with a register chip (RCD) that buffers address and control signals, allowing higher capacities (e.g., 32 GB) and is common in servers.

LRDIMM : Load‑Reduced DIMM adds a data buffer (DB) on top of the register, further increasing capacity at higher cost.

Images illustrate typical UDIMM, server RDIMM, and LRDIMM modules.

ECC Memory

DRAM is volatile and can suffer bit flips; a typical 8 GB module may see 1‑5 errors per hour. ECC (Error‑Checking and Correcting) adds an extra memory chip to detect and correct errors, using 72‑bit wide channels (64 bits data + 8 bits ECC). ECC memory is more expensive and slightly slower, but essential for server reliability.

Summary

Server CPUs are pricier partly because they support more memory channels (six in Skylake, eight in newer Xeon generations) and higher‑capacity DIMMs (RDIMM, LRDIMM) as well as ECC memory, unlike typical consumer CPUs which usually have two‑four channels and limited DIMM support.

Answers to the opening questions:

1. "6 channels" means the CPU can handle six independent memory channels, allowing parallel data transfers and higher aggregate bandwidth.

2. RDIMM and LRDIMM are buffered memory modules; RDIMM adds a register, while LRDIMM adds both a register and a data buffer, enabling larger capacities.

3. Bandwidth numbers are derived from the per‑channel calculation (21.33 GB/s) multiplied by the six channels to reach the theoretical 128 GB/s aggregate, though real‑world performance may be lower due to latency and other factors.