Linux’s multitasking illusion relies on CPU context switches, where the kernel saves and restores registers and program counters for processes, threads, and interrupts, and understanding these mechanisms—including their types, performance costs, and scheduling triggers—reveals why excessive switches can degrade system performance.
This article explores whether modern CPUs contain undocumented or hidden instructions, explains the challenges of searching the variable‑length x86 ISA, presents a depth‑first algorithm that skips irrelevant bytes, shows how to infer instruction length using page‑fault side‑effects, and reveals discovered hidden opcodes on Intel and AMD processors.
This tutorial shows how to create a Bash script that continuously monitors a Linux server’s memory, disk, and CPU usage, explains the commands used, demonstrates assembling the data into variables, looping for a set period, logging results, and optionally applying a stress test to generate load.
This article provides a step‑by‑step methodology for troubleshooting online service failures by systematically examining CPU, disk, memory (including heap, OOM, stack overflow, and off‑heap), garbage collection, and network problems using tools such as ps, top, jstack, jmap, jstat, iostat, vmstat, strace, and tcpdump.
This guide explains how to use the Linux top command to monitor real‑time process activity, interpret CPU, memory and swap statistics, customize displayed columns, apply command‑line options, and understand key metrics such as load average and steal time for effective system performance management.
The article investigates whether modern x86 CPUs contain undocumented or hidden instructions, explains how to search the instruction space using a depth‑first algorithm that leverages page‑fault side‑effects to determine instruction length, and presents the results of uncovering such hidden opcodes on Intel and AMD processors, highlighting the potential security risks.
This article explains what performance means, why optimization remains essential even on powerful multi‑core CPUs, large memory, and SSDs, and demonstrates through simple code examples how algorithmic complexity can cause noticeable lag, urging developers to prioritize performance tuning.
This article provides a comprehensive overview of server CPUs, covering core components, operation stages, performance parameters, Intel TurboBoost, Xeon Scalable naming, Tick‑Tock development, multi‑core and many‑core designs, hyper‑threading, heterogeneous computing, and the differences between CISC and RISC architectures.
This guide explains how to configure CPU and memory requests and limits for Kubernetes pods, implement QoS classes, use LimitRange and ResourceQuota, and monitor resource usage with Prometheus queries and Grafana dashboards to ensure stable cluster operations.
This article chronicles the origins, competition, legal battles, and strategic innovations of Intel and AMD from the 1950s semiconductor breakthroughs to recent market resurgence, illustrating how their rivalry shaped the modern CPU industry over more than half a century.
This guide explains Linux performance optimization by defining key metrics such as throughput and latency, clarifying average load, detailing CPU context switches, describing common performance analysis tools, and providing practical methods for diagnosing and improving CPU, memory, and I/O bottlenecks in production environments.
This guide explains Linux performance optimization by defining key metrics such as throughput and latency, describing how to interpret average load, and detailing step‑by‑step usage of tools like vmstat, pidstat, perf, and dstat to diagnose CPU, memory, I/O, and context‑switch bottlenecks.
This comprehensive guide explains Linux performance fundamentals, covering key metrics like throughput and latency, how to interpret average load, CPU context switching, memory management, and the most effective tools and techniques for diagnosing and optimizing system performance.
This guide explains Linux performance optimization by defining key metrics such as throughput, latency, average load, and CPU usage, describing how to select and interpret tools like vmstat, pidstat, perf, and dstat, and offering concrete steps to diagnose and fix CPU, memory, I/O, and context‑switch bottlenecks.
This article explains how a CPU handles interrupts using mechanisms like the programmable interrupt controller (PIC), advanced APIC, interrupt vectors, IDT, and how interrupt affinity and CPU affinity can be configured to balance load across multiple cores, illustrating both synchronous exceptions and asynchronous interrupts.
This guide explains Linux performance optimization by defining core metrics such as throughput, latency, and average load, describing how to select and benchmark indicators, outlining essential analysis tools like vmstat, pidstat, and perf, and providing practical CPU and memory tuning strategies to eliminate bottlenecks.
The article examines a puzzling StackOverflow case where sorting a random array before summation yields a six‑fold speedup, explains the phenomenon through CPU five‑stage pipeline fundamentals, structural, data, and control hazards, and shows how branch prediction and operand forwarding mitigate the performance loss.
China's domestic CPU industry, once nascent, has rapidly progressed through three phases—initial development, transition, and acceleration—producing key players such as Phytium, Kunpeng, Haiguang, Loongson, Zhaoxin, and Shenwei, each advancing performance, ecosystem, and security to challenge foreign incumbents.
Intel's new SDSi feature, now supported in Linux kernel 5.18, lets customers pay to unlock additional CPU cores and potentially other performance enhancements, a strategy originally designed for data‑center processors that could reshape how processor capabilities are monetized.
This article provides a comprehensive technical overview of server hardware architecture, covering the evolution from dual‑chip (MCH + ICH) to single‑chip (PCH) designs, detailed PCIe specifications, PCB and cooling considerations, and the power‑supply strategies used in modern data‑centers.
This guide explains why databases like TiDB have specific hardware requirements and provides detailed recommendations for CPU selection, memory tuning, storage choices, and network configuration to achieve optimal performance and cost efficiency.
This guide explains Linux performance optimization by defining key metrics such as throughput and latency, interpreting average load, exploring CPU context switches, and providing practical step‑by‑step instructions for using tools like vmstat, pidstat, perf, strace, and memory analysis utilities to diagnose and resolve CPU, I/O, and memory bottlenecks.
This guide explains Linux performance optimization by covering key metrics such as throughput, latency, load average, CPU context switching, and memory management, and demonstrates how to use built‑in tools like vmstat, pidstat, perf, and cachetop to diagnose and resolve bottlenecks.
Learn practical JVM tuning techniques by identifying high CPU usage, diagnosing deadlocks, and uncovering memory leaks using tools such as top, jstack, jps, jstat, and jmap, with step‑by‑step commands and code examples to help you optimize Java application performance.
This article compares Kubernetes pod monitoring metrics with traditional KVM/VM metrics across CPU, memory, disk, and network, explaining the underlying reasons for the differences and offering guidance on interpreting the data for effective performance troubleshooting.
Researchers at ETH Zurich introduce Exemplar Transformers, a novel Transformer layer that accelerates visual object tracking by eight times, runs in real‑time on CPUs, and improves robustness when integrated into a Siamese‑based tracker, achieving state‑of‑the‑art performance on six benchmark datasets.
dl_inference is an open‑source, production‑grade deep learning inference platform that supports TensorFlow, PyTorch and Caffe models, offering GPU and CPU deployment, TensorRT and MKL acceleration, multi‑node load balancing, and extensive Q&A on model conversion, hardware requirements, INT8 quantization, and performance gains.
The 2021 China Integrated Circuit Market Research Report analyzes recent three‑year trends showing rising shares of MPU and logic chips, declining DRAM, stable analog and MCU, and details the market status, growth forecasts, and challenges for CPU, GPU, FPGA, ASIC, and storage technologies.
This article provides a comprehensive overview of CPU caches, covering why they are needed, their classification, placement and lookup mechanisms, replacement and write policies, and coherence protocols such as MESI, illustrating each concept with diagrams and code examples.
This article explains how CPUs receive interrupt numbers through hardware, exceptions, or the INT instruction, describes the structure and purpose of the Interrupt Descriptor Table, and details the stack operations and control‑flow steps the processor performs to handle and return from an interrupt.
This article analyzes why Alipay’s cold start on our device is slower than on competing phones and presents a series of optimizations—including CPU boosting, Dex2oat strategy adjustments, GC frequency reduction, and I/O improvements—that collectively close the performance gap.
The 2021 China Integrated Circuit Market Research Report analyzes recent three‑year trends, showing rising shares for MPU and logic chips, declining DRAM, stable analog and MCU, while detailing the market positions, growth rates, and challenges of CPU, GPU, FPGA, ASIC, and flash storage technologies.
In a large‑scale Redis cluster, expanding nodes caused unexpected CPU spikes and higher latency for MGET operations, prompting a deep investigation that traced the issue to the CLUSTER SLOTS command and its handling of MOVED errors, followed by a code‑level optimization that reduced CPU usage by over 90% and cut command latency dramatically.
This article explains the motivation behind CPU caches, describes their placement in the memory hierarchy, details cache organization, placement policies, lookup mechanisms, replacement strategies, write handling, and coherence protocols such as MESI, providing a comprehensive overview of cache fundamentals.
The article summarizes AMD’s 2022‑2023 Zen 4 EPYC roadmap—including the 96‑core Genoa and 128‑core Bergamo processors built on TSMC’s 5 nm process, the new Zen 4c core for cloud‑native workloads, and Intel’s parallel IDM 2.0 plan—while providing cache specifications, performance claims, and links to further technical resources.
This article explains the fundamental principles of computer operation, covering CPU architecture, memory organization, instruction execution, compiler translation, caching strategies, and the role of operating systems, while illustrating concepts with diagrams and code examples.
The article provides a comprehensive analysis of China's domestic CPU ecosystem, examining the technical distinctions between architectures and instruction sets, the security implications of relying on foreign designs, and the strategic balance needed between indigenous development and imported technologies to advance the nation's semiconductor industry.
This article explains the basic principles of computer architecture, covering CPU operation, memory organization, binary representation, instruction sets, caching levels, storage hierarchy, compilers, script languages, and the impact of open‑source software on system design.
This article explains the basic principles of how computers work, covering CPU and memory organization, instruction sets, endianness, compiler role, operating system interaction, cache levels, storage technologies, and performance optimization techniques.
This guide walks through installing the Go‑based Node Exporter, configuring it as a systemd service or Docker container, exposing standard Prometheus metrics, and using PromQL to calculate CPU usage across multiple nodes.
This article explains theoretical formulas and practical guidelines for calculating the optimal thread pool size in Java, covering CPU‑bound and I/O‑bound workloads, how to measure CPU cores and blocking ratios, and provides example calculations and code snippets.
The article analyzes the current X86 market dominance of Intel, AMD's rapid advancement with its Zen architecture and 7nm process, the competitive landscape of server and consumer CPUs, and the emergence of Chinese domestic processors built on licensed X86 technology.
This article provides a comprehensive analysis of CPU architecture evolution, workflow, historical milestones, CISC versus RISC competition, the emergence of RISC‑V, China's domestic processor initiatives, and current market share trends across servers, desktops, and mobile devices.
The article explains the fundamental role of CPUs in modern computing, reviews their historical development, analyzes the current market dominated by foreign giants, highlights policy‑driven growth of domestic processors, and outlines how emerging fields like 5G, cloud, AI and IoT create new demand and opportunities for CPU innovation.
This article explains the fundamentals of x86 interrupt handling, covering the distinction between interrupt vectors and descriptors, classification of internal and external interrupts, the role of the 8259A PIC, how interrupt numbers are assigned, and the mechanisms for saving and restoring CPU state during an interrupt.
This article explains how to identify and resolve server CPU spikes caused by excessive DateTime object creation in a Java application, detailing step‑by‑step Linux command usage, JStack and JProfiler analysis, and a refactoring solution that replaces DateTime comparisons with string comparisons to reduce GC pressure.
The article explains how V8’s built‑in methods, originally placed far from JIT‑generated code, cause costly branch‑prediction failures on 64‑bit CPUs, and how copying these snippets into a nearby memory region reduces mispredictions and improves performance at a modest memory cost.
An avid creator spent six months hand‑soldering thousands of transistors, diodes, and resistors to assemble a working 6‑bit CPU, detailing the design of its shift register, program counter, ROM/RAM modules, instruction decoder, ALU, and the challenges of debugging its binary code.
This article explains why a CPU with only a few small registers can still operate on massive in‑memory data structures by loading one element at a time using load/store instructions and how compilers strategically allocate registers to minimize memory traffic.
This article explains the meaning of each CPU usage field shown by the top command, dives into the Linux kernel source that records these metrics via clock interrupts, and shows how the percentages are computed from /proc/stat data.
This guide explains how to allocate CPU and memory to containers and pods in Kubernetes, clarifies resource units, demonstrates practical Deployment, ResourceQuota, and LimitRange configurations with YAML examples, and lists useful tools for monitoring and enforcing resource constraints.
The article explains CPU utilization and CPU load, clarifies time‑slice concepts, distinguishes user‑mode and system‑mode usage, describes how load reflects the average number of runnable and waiting tasks, and provides Linux commands and troubleshooting steps for high‑load/low‑utilization and vice‑versa scenarios.
This guide walks you through systematic troubleshooting of Java production issues—covering CPU, memory, disk, GC, and network problems—by using tools like jstack, jmap, top, iostat, vmstat, and netstat to pinpoint root causes and apply targeted fixes.
This article provides a comprehensive introduction to the fundamentals of x86 Linux, covering the historic Intel 8086 processor, segment descriptors, main memory organization, registers, bus architecture, CPU addressing modes, control mechanisms, and the basic instruction execution cycle.
This article explains how CPU core count versus clock speed and memory size influence MySQL performance, discusses when to prioritize multi‑core or high‑frequency CPUs for concurrency or query speed, and offers practical guidelines for selecting server hardware based on workload characteristics.
An in‑depth guide walks you through every stage of CPU production—from extracting pure silicon from sand, melting and shaping ingots, slicing wafers, applying photoresist, performing photolithography, ion implantation, metal layering, testing, and final packaging—revealing the complex, multi‑billion‑dollar process behind modern processors.
This article explains the difference between CPU utilization and CPU load, describes how to interpret these metrics, and provides practical Linux commands and step‑by‑step methods for diagnosing high load with low utilization or vice versa, including common I/O and indexing issues.
This guide shows Linux users how to retrieve detailed CPU information—including model, frequency, physical and logical core counts, and hyper‑threading status—by querying /proc/cpuinfo with simple command‑line filters.
This article explains how to allocate CPU and memory to containers and Pods in Kubernetes, covers ResourceQuota and LimitRange mechanisms, provides practical YAML examples, and lists useful tools for monitoring and enforcing resource constraints.
This article explains how a single transistor acts as a switch, how combining AND, OR, and NOT gates yields logical completeness, how binary addition is built from these gates, and how registers, memory, instruction sets, and clock signals together form a functional CPU.
This guide walks through systematic troubleshooting of Java server problems—including CPU spikes, memory leaks, disk I/O bottlenecks, and network timeouts—by using native Linux tools and JVM utilities such as ps, top, jstack, jstat, iostat, vmstat, and netstat to pinpoint root causes and apply targeted fixes.
This article explains the fundamental principles and workflow of building an NES (Family Computer) emulator, covering ROM loading, memory mapping, CPU and PPU collaboration, graphics rendering, sprite handling, palette management, and interrupt processing with illustrative code examples.
This guide lists essential Linux commands for retrieving comprehensive hardware information—including CPU, memory, disk, network interfaces, PCI, USB, SCSI, and BIOS details—along with example outputs and explanations for each category on an Ubuntu 16.04 system.
This article explains the core principles of building a Nintendo Entertainment System (NES) emulator, covering the collaboration of CPU, PPU, and APU, memory mapping, ROM loading, instruction decoding, graphics rendering, and interrupt handling, with practical code examples.
CPUFetch is a cross‑platform command‑line utility that reports CPU architecture, model, microarchitecture, nanometer technology, frequency, core/thread count, AVX/FMA support, cache sizes, and peak performance, and this guide explains how to compile, install, run, and uninstall it on Ubuntu (and other OSes).
This article explains how the invention of assembly‑line manufacturing parallels modern CPU pipelines, why processing an ordered array can be nearly ten times faster than an unordered one, and shows a practical bit‑wise optimization to eliminate costly if‑statements for high‑performance code.
This guide explains how to use Linux command‑line utilities such as free, vmstat, top, sar, iostat, iotop, netstat, and jstack to identify memory, CPU, network, and disk performance bottlenecks, and provides practical commands for monitoring and troubleshooting each resource.
The article provides a comprehensive analysis of China’s Xinchuang industry in 2023, detailing its $104.3 billion market size, the domestic CPU ecosystem, operating system adoption, database and middleware players, and the rapidly growing information‑security sector driven by cloud and IoT technologies.
This article examines how computing power has become a key production factor, detailing the shift from traditional CPUs and GPUs to specialized processors like DPUs, and explores emerging paradigms such as in‑memory, near‑memory, and edge computing that reshape data‑center architectures.
This guide walks through a systematic four‑step approach—CPU, disk, memory, and network—to pinpoint Java service failures using tools like jstack, jmap, top, vmstat, iostat, jstat, netstat, ss, and tcpdump, covering OOM, GC, off‑heap, and TCP state problems.
This guide explains how to allocate and control CPU and memory for containers and Pods in Kubernetes, covering resource units, request and limit settings, ResourceQuota objects, LimitRange defaults, practical YAML examples, and useful monitoring tools.
This article provides a thorough, step‑by‑step guide to using the Linux sar command for real‑time and historical monitoring of CPU, memory, I/O, and network statistics, including syntax, sample outputs, installation tips, common pitfalls, and data‑export techniques.
An overview of the CPU’s pivotal role in IT systems leads into a four‑point framework for domestic processors, covering ARM’s market dominance, the semiconductor supply chain, three development pathways—X86 licensing, ARM licensing, and self‑designed architectures—and the security‑driven outlook shaping China’s future CPU landscape.
The article examines the rapid growth of data‑center workloads, explains why heterogeneous accelerators such as CPUs, GPUs, FPGAs and ASICs are needed, outlines evaluation standards, compares their compute performance and power efficiency, and discusses practical deployment cases and future trends.
This article provides a step‑by‑step guide for diagnosing Java production issues by systematically checking CPU usage, disk health, memory consumption, garbage‑collection behavior, and network problems using common Linux tools and JVM utilities such as ps, top, jstack, jstat, vmstat, iostat, free, jmap, and tcpdump.
This article examines the rise of ARM and other CPU architectures in China, outlines three paths to domestic CPU development, profiles key players such as Huawei, FeiTeng, and Amazon, and evaluates the emerging ARM server ecosystem and its competitive stance against x86.
This article explains CPU architecture, cache hierarchy, the concept of cache lines, how false sharing degrades performance, mitigation techniques like cache‑line alignment, and the Linux scheduler's task prioritisation, virtual runtime, and run‑queue mechanisms for fair and real‑time execution.
The article explains how data moves through server motherboards, the role of CPUs, chipsets, and buses, the impact of platform upgrades on memory, GPU, SSD and power solutions, and how Intel's Xeon roadmap drives performance, pricing, and overall server market trends.
This article provides a comprehensive overview of the development, major manufacturers, architectures, performance specifications, ecosystem building, and security features of China's domestic CPUs, tracing their historical evolution from the 1950s to the present and assessing their role in national technology independence.
The article narrates a whimsical tour through CPU history, explaining how the 8086 used shared address/data pins and segmentation, how 32‑bit processors introduced separate buses and operating‑system multitasking, and how virtual memory, paging, and swapping evolved to support modern multi‑core systems.
This guide explains how to use Prometheus' irate function and Grafana to calculate and visualize CPU, memory, and disk usage percentages for each host, including the necessary PromQL queries and formulas in a monitoring setup.
The article explains the data flow and component interactions on server motherboards, details CPU and chipset roles, describes Intel's successive CPU platforms and manufacturing processes, and analyzes how these technological upgrades influence server configurations, market demand, and datacenter growth.
This guide walks you through essential Linux server configuration checks—retrieving OS version, kernel, CPU specs, memory usage, and disk information—using common command‑line tools, helping administrators quickly understand hardware and system details for effective deployment and maintenance.
This article explains the role of CPU cache in modern processors, covering its types, how it works within the memory hierarchy, the differences among L1, L2, and L3 levels, and the impact of cache hits, misses, and latency on overall system performance.
This article explains the role of CPU cache in modern processors, covering its purpose, the memory hierarchy, the differences between L1, L2, and L3 caches, how cache hits and misses affect latency, and future trends such as larger and on‑chip caches.
This article explains what CPU cache is, why it matters for processor performance, how it works within the memory hierarchy, the differences among L1, L2, and L3 caches, the impact of cache hits and misses on latency, and emerging trends in cache design.
This comprehensive guide explores the myriad x86/x64 CPU registers—including general, flag, instruction, segment, control, debug, descriptor, task, and model‑specific registers—explaining their roles, how they interact in memory addressing, multitasking, system calls, and debugging, while highlighting key differences between 32‑bit and 64‑bit modes.
Hard drives (HDD) and solid‑state drives (SSD) differ dramatically in latency; the article explains the orders‑of‑magnitude gap between CPU cache, memory, and disk access, details the I/O mechanisms (programmed I/O, interrupt‑driven I/O, DMA), and shows why mechanical drives are inherently slow.
This guide details a systematic approach to diagnosing Java service failures by sequentially checking CPU, disk, memory, and network issues, using tools like ps, top, jstack, jstat, iostat, jmap, and netstat to pinpoint root causes and apply appropriate fixes.
This article explains the fundamental hardware components of a CPU, starting with early relay‑based machines, describing basic logic gates, constructing simple adders and an ALU, detailing memory and registers, and illustrating the fetch‑decode‑execute cycle and the evolution of machine code to assembly language.
This article explains how to monitor and interpret CPU usage and load average on Linux servers, details the calculations behind these metrics, illustrates their meaning with examples and images, and provides step‑by‑step troubleshooting methods for high load, high CPU, and high load with low CPU scenarios.
This article provides a systematic, step‑by‑step guide for diagnosing and resolving Java runtime problems—including CPU spikes, memory leaks, disk I/O bottlenecks, network timeouts, and GC inefficiencies—by using native Linux tools and JVM utilities such as top, ps, jstack, jmap, jstat, iostat, vmstat, pidstat, netstat, ss, and tcpdump.
This article provides a systematic, step‑by‑step guide for diagnosing Java production incidents by examining CPU, disk, memory, GC, and network layers, illustrating the use of tools such as jstack, jmap, jstat, vmstat, iostat, netstat, ss, and tcpdump with concrete command examples and visual aids.
This article examines the challenges of existing stream‑processing benchmarks, introduces the open‑source Nexmark framework designed for reproducible, comprehensive performance testing, describes its metrics, query set, workload configurability, and presents experimental results on Flink, highlighting its role in advancing big‑data stream benchmarking.
This article provides a comprehensive overview of server hardware fundamentals, covering server form factors, motherboard architecture, selection criteria, major vendors, CPU concepts and performance, NUMA, memory specifications, disk throughput and IOPS, as well as network card types and bonding modes.
This article provides a step‑by‑step troubleshooting guide for Java production incidents, covering CPU, disk, memory, GC, and network problems with practical commands, analysis techniques, and tools such as jstack, jmap, iostat, netstat, and native memory tracking.
This article provides a detailed, step‑by‑step methodology for diagnosing and resolving common Java production problems—including CPU spikes, disk bottlenecks, memory leaks, garbage‑collection anomalies, and network timeouts—by leveraging native Linux tools and JVM utilities such as ps, top, jstack, jmap, jstat, iostat, vmstat, pidstat, and netstat.
The article uses a factory metaphor to explain CPU clock generation, instruction dependencies, resource idle time, and how hyper‑threading attempts to improve utilization, while also highlighting its limitations and impact on power consumption.
The article reviews three major IT events—Docker's new service terms restricting entities on the US Commerce Department list, Nvidia's potential ARM acquisition and its impact on AI and supercomputing, and Intel's latest CPU and GPU technologies—while also explaining CPU fundamentals, CISC vs. RISC architectures, and the current state of China's domestic processor industry.
This article explains the CPU's interrupt mechanism, describing how hardware devices trigger interrupts, the role of the 8259A programmable interrupt controller, the evolution to APIC with I/O and Local APICs, and how interrupt affinity can be configured to improve multi‑core performance.
