Interrupt Mechanism, PIC, APIC, and Interrupt Affinity Explained

I am "CPU Workshop" A‑Q, and our daily job is to continuously execute code instructions while interacting with other units attached to the motherboard such as the keyboard, mouse, disk, and network card.

When any of these units needs our attention, it sends an interrupt signal that lights up a lamp; after each instruction we check the lamp, and if it is on we suspend the current work, save the current registers and execution state on the stack, and handle the interrupt.

Sometimes we do not want to be interrupted; we set a flag in the eflags register—1 allows interrupts, 0 masks them.

There is also a non‑maskable interrupt ( NMI ) that cannot be blocked, typically used for critical events such as power loss, overheating, or bus errors.

8259A PIC

Because many devices may request service, the system uses a programmable interrupt controller (PIC), known as 8259A, to receive interrupt requests. Each device is assigned an interrupt vector number, and the Interrupt Descriptor Table (IDT) stores the address of the handler function for each vector. The IDTR register points to the IDT, which is placed in memory.

Exceptions (e.g., division by zero, invalid memory access) are also looked up in the same table; handling an exception is synchronous, whereas handling an interrupt is asynchronous.

APIC

When the system grew from a single‑core to multi‑core CPU, the 8259A PIC could not keep up, so it was replaced by the Advanced Programmable Interrupt Controller (APIC). APIC consists of an I/O APIC that receives external interrupt requests and distributes them to Local APICs embedded in each core.

The I/O APIC forwards interrupts to the appropriate Local APIC, allowing each of the eight cores to process them independently. APIC also supports Inter‑Processor Interrupts (IPI) for cores to signal each other.

Interrupt Affinity

During heavy network traffic, the network card generates many interrupts that were being handled by a single core, causing overload. By configuring interrupt affinity, the system can assign specific interrupts to particular cores, balancing the load.

The operating system provides an API (e.g., smp_affinity ) that lets threads and interrupts declare their preferred CPU masks, enabling flexible and efficient distribution of work across cores.