1 views collected around this technical thread.
This article explains how a CPU handles interrupts using mechanisms like the programmable interrupt controller (PIC), advanced APIC, interrupt vectors, IDT, and how interrupt affinity and CPU affinity can be configured to balance load across multiple cores, illustrating both synchronous exceptions and asynchronous interrupts.
The article explains how Position Independent Code (PIC) enables code to run at any address using GOT and PLT tricks, how Position Independent Executables (PIE) extend this to whole binaries, and how Linux’s Address Space Layout Randomization (ASLR) leverages PIE to fully randomize process memory, making exploitation significantly harder.
This article explains the CPU's interrupt mechanism, describing how hardware devices trigger interrupts, the role of the 8259A programmable interrupt controller, the evolution to APIC with I/O and Local APICs, and how interrupt affinity can be configured to improve multi‑core performance.