This article explains ARMv8‑A AArch64 virtualization support, covering Stage 2 page‑table translation, virtual exceptions, traps, hypervisor types, memory management, device emulation, interrupt handling, clock virtualization, VHE, nested virtualization, and the performance overhead of context switches.
Arm's newly revealed Armv9 architecture introduces major ISA extensions, a confidential compute model, AI‑focused vector capabilities, and performance road‑maps that together aim to unify mobile, server and future workloads while strengthening security and software ecosystem compatibility.
An extensive analysis traces the evolution of CPU architectures—from early Intel 4004 to modern x86, ARM, RISC‑V and MIPS—examining their technical differences, market shares, recent performance gains, and the shifting competitive landscape across servers, desktops, mobile devices, and emerging IoT applications.
Servers, the high‑performance backbone of cloud and data‑center infrastructures, differ from ordinary PCs in stability, hardware, and firmware; they come in various logical and physical forms, are classified by architecture, CPU count, and application, and the market now sees a competitive split between X86 and ARM designs.
Developers have managed to boot Windows 11 on Android smartphones, Raspberry Pi 4, and even a legacy Lumia device, revealing both the technical breakthroughs and the remaining limitations such as missing phone functions and reliance on custom UEFI ports.
This article explains the low‑level principles of C++ coroutine context switching, walks through the owl.context API design, demonstrates assembly implementations for co_getcontext, co_setcontext, co_swapcontext and co_makecontext, and provides practical examples and code to build stackful coroutines on 32‑bit ARM.
Memory Tagging Extension (MTE), introduced in ARM v8.5, tags memory with 4‑bit keys and checks them in hardware via synchronous or asynchronous modes, providing low‑overhead detection of use‑after‑free, overflow and underflow bugs in Android (since 12) and Linux kernels, complementing tools like ASan and KASAN despite a 16‑byte granularity limitation.
This article provides a comprehensive analysis of CPU architecture evolution, workflow, historical milestones, CISC versus RISC competition, the emergence of RISC‑V, China's domestic processor initiatives, and current market share trends across servers, desktops, and mobile devices.
The article explains the Linux kernel boot process on ARM platforms, covering how the bootloader loads and decompresses the gzipped kernel image, the entry points of the compressed zImage, the early serial output, the initialization of the MMU and page tables, and the transition to the main C kernel code.
This article explains the GCC compiler suite, its internal packages (Binutils, gcc‑core, Glibc), demonstrates a simple C build, and details cross‑compilation techniques for ARM, including differences between arm‑linux‑gcc, arm‑elf‑gcc, and various C libraries such as uClibc and newlib.
At the 2021 ACM China Turing Conference in Hefei, leading academics and industry experts presented cutting‑edge research on AI‑driven security, mobile OS vulnerability detection, IoT sensor risks, ARM confidential computing, and zero‑trust frameworks, highlighting how emerging technologies reshape secure mobile and industrial ecosystems.
This article explains the GNU Compiler Collection (GCC) architecture, its core packages (Binutils, gcc‑core, Glibc), demonstrates a simple C compilation workflow, and details cross‑compilation techniques for ARM including arm‑linux‑gcc, arm‑elf‑gcc, and various C libraries such as uClibc and newlib.
The article examines edge computing hardware architecture, discussing diverse use cases, evolving server and processor trends—including ARM, Intel, Nvidia, AMD, FPGA, and DPU—open hardware standards, reliability, virtual networking, and storage innovations, highlighting how these developments shape the future of cloud and edge infrastructures.
This article explains how U‑Boot loads the device‑tree blob into memory, transfers its address via the r2 register using either bootm_header_t or legacy boot parameters, and describes the kernel’s two‑stage parsing process that validates, scans, and unflattens the tree into device nodes.
This tutorial walks you through the Linux kernel source layout, required build tools, cross‑compilation setup, how to compile a kernel image, generate device‑tree blobs, build standalone .ko modules, and integrate those modules into a custom kernel for ARM boards.
The article explains how the Windows 11 preview can be installed on Snapdragon‑based Android phones and Raspberry Pi devices via the community‑driven Renegade Project, detailing the required tools, current device support, encountered limitations, and the broader implications for ARM‑based Windows deployments.
The article reports on community efforts to install the Windows 11 ARM64 preview on Android smartphones and Raspberry Pi devices, describing the Renegade Project, successful deployments on OnePlus 6T and Xiaomi 8, remaining limitations, and the required hardware and firmware modifications.
This article explains Android native stack unwinding methods, compares frame‑pointer and exception‑handling approaches, proposes performance‑focused simplifications, shows how to traverse JNI, OAT and JIT frames, and introduces the Quicken Unwind Table (QUT) that can speed up backtraces by up to 30×.
This article examines Ceph’s architecture, identifies performance bottlenecks on Huawei’s Kunpeng ARM platform, and presents practical tuning methods—including NUMA placement, cache tagging, vector acceleration, thread scaling, and monitoring tools—to improve storage efficiency, reduce latency, and lower power consumption.
This article analyzes the shift from x86 to ARM architectures in cloud environments, covering instruction‑set differences, migration stages such as virtualization, containerization and cloud‑native adoption, language‑specific impacts, and a practical case study of the Lanxin application on China Electronic Cloud.
This guide explains how to install and run the DBLE distributed database middleware on Huawei's Kunpeng 920 ARM‑based servers, covering wrapper preparation, Kunpeng‑compatible JDK installation, DBLE startup verification, and connection testing with MySQL client.
This article explains the shift from x86 to ARM architectures, outlines why services should be migrated to ARM‑based Kunpeng cloud servers, describes Huawei's migration tools and community support, and provides concrete C/C++ migration examples and common pitfalls for backend developers.
This article provides a comprehensive overview of ARM's processor architecture, its ecosystem and business strategy, recent product releases such as Cortex‑A78, Cortex‑X1 and Mali‑G68, as well as the company's role in AIoT, automotive and cloud computing markets.
This article examines the rise of ARM and other CPU architectures in China, outlines three paths to domestic CPU development, profiles key players such as Huawei, FeiTeng, and Amazon, and evaluates the emerging ARM server ecosystem and its competitive stance against x86.
This article provides a comprehensive overview of servers, covering their definition, hardware and firmware composition, various classification schemes (form factor, instruction set, processor count, application type), and the ongoing market competition between X86 and ARM architectures.
Nvidia’s $40 billion purchase of Arm from SoftBank merges its AI chip expertise with Arm’s vast processor ecosystem, promising new AI research centers, open licensing, and a strategic edge against rivals while reshaping the future of computing hardware.
This article examines the security challenges of Android and IoT devices built on ARM/ARM64 platforms, explains how Google's Generic Kernel Image (GKI) restricts kernel modifications, and provides detailed techniques—including memory‑page attribute manipulation, remap_pfn_range, and assembly‑level hook implementations—to safely inject custom functionality into the kernel while addressing write‑protection, concurrency, and module‑unloading issues.
This article examines the rise of ARM‑based CPUs, details AWS's Graviton 2 processor and its deployment in M6G instances, and presents extensive performance, cost, and third‑party benchmark comparisons to illustrate the emerging shift toward ARM in cloud computing.
The article reviews the historical shift from mainframes to x86, highlights the emerging limitations of x86 in the era of mobile and cloud workloads, and details how Huawei's ARM‑based Kunpeng platform and its migration toolchain enable efficient cross‑architecture software migration and performance optimization.
The article reviews three major IT events—Docker's new service terms restricting entities on the US Commerce Department list, Nvidia's potential ARM acquisition and its impact on AI and supercomputing, and Intel's latest CPU and GPU technologies—while also explaining CPU fundamentals, CISC vs. RISC architectures, and the current state of China's domestic processor industry.
This article surveys the development of server hardware, comparing CISC‑based x86 CPUs that currently dominate the market with emerging ARM‑based RISC designs, and examines how Chinese domestic processors and cloud providers are reshaping the server ecosystem through performance, power efficiency and licensing strategies.
This article provides an in‑depth overview of servers, covering their definition, logical and hardware architecture, firmware and operating systems, various classification schemes (form factor, instruction set, processor count, application type), and a detailed comparison of X86 and ARM server platforms.
The article reviews recent ARM breakthroughs—including the Fugaku supercomputer topping the TOP500 list, Apple's transition to custom ARM chips, Ampere's high‑core Altra processors, a detailed X86 vs ARM analysis, and Huawei's Kunpeng ecosystem—highlighting ARM's growing influence in servers, PCs, and cloud computing.
With the rise of mobile, IoT, and edge computing, the long‑standing dominance of x86 is challenged, prompting developers to migrate applications to ARM‑based Kunpeng platforms; this article explains the architectural differences, a five‑step migration methodology, and detailed C/C++ compilation considerations including instruction, macro, and SIMD adaptations.
On June 22, 2020, Japan's Fugaku supercomputer, built with Fujitsu's ARM‑based A64FX processors, claimed the top spot in all four TOP500 benchmarks, delivering 415.5 petaflops in Linpack and dramatically surpassing rivals while highlighting the growing impact of ARM architecture in high‑performance computing.
This article explains what a server is, its logical and hardware architecture, the role of firmware and operating systems, various classification methods—including form factor, instruction set, processor count and application type—and compares the market dynamics and technical advantages of X86 and ARM servers.
This article provides a detailed introduction to server fundamentals, covering what servers are, their logical and hardware architecture, firmware and operating systems, various classification schemes, and the ongoing competition between X86 and ARM server platforms in the data‑center market.
This article provides a comprehensive overview of ARM's history, core architecture, business strategies, recent CPU and GPU releases, and its positioning in AIoT, cloud computing, and emerging markets, highlighting both technical details and market-oriented initiatives.
The article examines the historical shift from mainframes to x86, highlights the emerging limitations of x86 in the era of mobile and cloud computing, and presents Huawei's ARM‑based Kunpeng platform with its performance advantages, ecosystem support, and step‑by‑step tools for migrating Java, Python, C/C++ and Go applications from x86 to ARM.
postmarketOS, an Alpine‑Linux based OS for legacy smartphones, now runs on roughly 200 mobile devices, highlighting the challenges of ARM porting, the role of pmbootstrap tools, and the community’s drive to extend device lifespans despite hardware and driver hurdles.
This article explains the shift from X86 to ARM server architectures, the motivations for moving services to ARM cloud platforms, the challenges of instruction‑set differences, and provides concrete migration practices and tooling support from Huawei's Kunpeng ecosystem.
This article explains the purpose and usage of key ARMv8-A registers—including general‑purpose, stack‑pointer, SIMD/floating‑point, program status, link, and program counter registers—while detailing their encoding, access modes, and relevance to exception levels.
This article provides a comprehensive overview of the ARMv8‑A architecture, explaining its RISC characteristics, execution states, instruction sets, register usage, and addressing modes, helping readers grasp the fundamentals needed to run operating systems like openEuler on ARM‑compatible servers.
The article examines the historical shift from mainframes to x86, highlights the emerging need for ARM-based solutions like Huawei's Kunpeng processors, and provides detailed migration strategies, tools, and best‑practice steps for moving C/C++ and other workloads from x86 to ARM architectures.
This article explains the fundamental differences between CISC and RISC processor designs, outlines their respective advantages and drawbacks, and compares three major CPU architectures—x86, ARM, and MIPS—highlighting their histories, features, and typical application domains.
Learn how to compile Redis from source and install it on an ARM-based system running Euler OS 2.8, covering environment setup, dependency building, configuration, service startup, and basic testing with redis-cli, demonstrating that the process mirrors standard installations.
The article provides a detailed comparison between ARM's RISC-based processors and Intel's x86 CISC architecture, covering design philosophy, performance, power consumption, expansion capabilities, operating system compatibility, software development tools, and cost considerations for various terminal applications.
This guide explains how to build an ARM GCC cross‑compilation toolchain on non‑ARM (x86) servers, covering environment preparation, toolchain download, installation steps, environment variable configuration, and testing the compiled binaries on a Kunpeng cloud server.
This article traces the origins of ARM from its 1978 founding, outlines the evolution of its classic and Cortex processor families, and explains the distinctions among application, real‑time, and microcontroller processors, providing a concise overview of ARM’s product classifications.
This article provides a comprehensive overview of ARM's evolution from ARMv1 to ARMv8, explains the distinction between architecture and core, details the features of each version, outlines the naming conventions of ARM processors, and describes the typical applications of various ARM cores such as ARM7, ARM9, ARM11, and Cortex series.
This article provides a comprehensive overview of the origins, market evolution, and technical characteristics of PowerPC, x86, and ARM processors, comparing their performance, power consumption, vector capabilities, and ecosystem support while highlighting why each architecture succeeded or struggled in the industry.
This article explains the fundamental differences between RISC and CISC architectures, reviews the historical development and technical characteristics of processors such as MIPS, ARM, and x86, and discusses why China’s Loongson chips favor the MIPS instruction set over alternatives.
This article summarizes the latest 2020 processor announcements from ARM, Intel, and AMD, highlighting ARM's Cortex‑A77 and Mali‑G77 designs, Intel's 10 nm Ice Lake and Athena initiatives for thin laptops, and AMD's Ryzen 3000 7 nm lineup, while comparing their differing strategies for the future of computing.
The article provides a comprehensive overview of RISC principles and compares major processor families—including ARM, x86, Atom, MIPS, and PowerPC—detailing their architectures, performance characteristics, market adoption, and licensing models while also mentioning related DSP technologies and reference resources.
This article provides a detailed comparison between ARM's RISC-based processors and Intel's CISC‑based x86 CPUs, covering design philosophies, performance, power consumption, expansion capabilities, operating‑system compatibility, software development tools, cost factors, and suitable application scenarios.
This article examines why converting a double value that exceeds the long range yields opposite signs on x86 and ARM processors, explains the underlying CPU instruction differences, presents detailed conversion tables, and reviews essential floating‑point and two's‑complement integer concepts.
This article chronicles the development of the x86 and ARM ecosystems, detailing early competitors, strategic alliances, technological shifts, market battles, and future trends that have shaped the semiconductor industry and the broader computing landscape.
This article provides a comprehensive overview of RISC architecture and its major implementations—including ARM, x86/Atom, MIPS, and PowerPC—detailing their design principles, performance characteristics, market adoption, and relevance to embedded and mobile systems.
This article chronicles the development, competition, and strategic shifts of the x86 and ARM processor ecosystems from their early days through recent innovations, highlighting key architectural decisions, market dynamics, and the evolving role of software abstraction layers in shaping the semiconductor landscape.
This article chronicles the origins of ARM from its 1978 Cambridge roots, the development of RISC architecture, the strategic shift to IP licensing, and how ARM's low‑power designs propelled it to dominate mobile, IoT, and computing ecosystems worldwide.
This article explains the principles of Reduced Instruction Set Computing (RISC), compares its performance advantages over Complex Instruction Set Computing (CISC), and surveys major RISC families such as ARM, MIPS, PowerPC, as well as Intel's low‑power Atom line and their roles in modern devices.
ARM has introduced the Neoverse N1 and E1 platforms, built on a 7nm process to deliver high scalability, performance and power efficiency for 5G, IoT and next‑generation cloud‑to‑edge infrastructure, while sparking debate among industry leaders about the future of server architectures.
Arm announced its upcoming Neoverse N1 platform and E1 CPU, sparking a heated debate with Linus Torvalds over ARM versus x86 server dominance, while developers like antirez argue for ARM's growing viability in server and cross‑development scenarios.
The article outlines Huawei's development of ARM‑based server CPUs, especially the 7nm Hi1620 processor, detailing its architecture, core counts, cache hierarchy, memory and I/O capabilities, and its significance for modern data‑center and cloud computing workloads.
The article offers a comprehensive, historically grounded analysis of the x86 and ARM ecosystems, tracing their origins, competitive battles, technical innovations, market shifts, and future challenges while highlighting why software ecosystems, licensing models, and emerging technologies shape CPU dominance.
This article explains how Alibaba's Pandora Lab discovered a kernel space mirroring vulnerability in Android 8 that defeats PAN and KASLR defenses, allowing arbitrary kernel writes and full system compromise through precise page‑table manipulation and a single‑write primitive.
This article traces the origins of ARM from its 1978 founding as Cambridge Processor Unit, through Acorn’s early microcontroller projects, the development of the RISC architecture, the creation of the ARM licensing model, and its rise to dominate mobile and embedded computing worldwide.
This article examines why an inline hook created with Substrate on ARM Thumb crashes, detailing the hook mechanism, the offending PC‑relative ADR instruction, and the necessary instruction fixes to prevent control‑flow errors.
This article breaks down the Samsung clock implementation in the Linux kernel, explaining the key fields of the clk structure, its operation callbacks, and the lookup table, while providing annotated code snippets and screenshots to illustrate each component.
This article examines the Linux kernel’s implementation of atomic variables on ARM architectures, detailing how the LDREX and STREX instructions provide atomicity in both UP and SMP systems, analyzing source code from arch/arm/include/asm/atomic.h, and illustrating various concurrency scenarios with diagrams and step‑by‑step explanations.
Google's Go 1.5 release replaces the traditional C compiler with a native Go compiler, introduces major performance and garbage‑collection improvements, and crucially adds support for the ARM architecture that dominates smartphones, enabling developers to write high‑performance mobile applications in Go.
