Overview of ARM Architectures and Core Product Models

1. ARM Architecture and ARM Cores

1.1 Brief Introduction to ARM Architecture and Cores

To date, ARM has released eight architecture versions: ARMv1, ARMv2, ARMv3, ARMv4, ARMv5, ARMv6, ARMv7, and ARMv8. These represent different instruction‑set versions.

Based on each architecture, different core processors can be designed. For example, the ARMv3 architecture gave rise to the ARM6 and ARM7 cores, which share the same instruction set but target different scenarios.

An analogy: early on, a simple house (architecture ARMv5) was built; later a version with a private bathroom (core ARM7) was added, and eventually a version with a small yard (core ARM9) was created.

Thus, ARMv1/2/3 etc. denote the instruction‑set architecture, while ARM7/9 etc. denote specific core implementations built on those architectures. All ARM architectures are based on the RISC instruction set.

1.2 Differences Between ARM Architecture Versions

1.2.1 ARM Version I (V1)

The V1 architecture appeared only in the prototype ARM1, featuring a 26‑bit address space and no commercial use. Key features include basic data‑processing instructions (no multiplication), byte/half‑word/word load‑store, sub‑routine call/link, software interrupt (SWI), and a 64 MB address space.

1.2.2 ARM Version II (V2)

V2 expanded on V1, adding 32‑bit multiplication, coprocessor instructions, and fast interrupt mode. Variants such as ARM2 and ARM3 (V2a) introduced on‑chip cache. The address space remains 64 MB.

1.2.3 ARM Version III (V3)

The first commercial ARM processor (ARM6) used V3, featuring on‑chip cache, MMU, and write buffer. Variants V3G and V3M added signed/unsigned multiply‑accumulate instructions with 64‑bit results. Notable changes: 32‑bit address space (4 GB), CPSR replacing R15 for program status, addition of SPSR, new exception modes, MRS/MSR instructions, and enhanced exception‑return instructions.

1.2.4 ARM Version IV (V4)

V4 built on V3 and is the most widely used architecture (ARM7, ARM8, ARM9, StrongARM). It removed the mandatory 26‑bit compatibility, added half‑word and byte load/store, introduced Thumb (16‑bit) instruction set, refined SWI, and added undefined‑instruction trapping.

1.2.5 ARM Version V (V5)

Based on V4, V5 added BLX (branch with link and exchange), CLZ (count leading zeros), BRK interrupt, DSP extensions (V5TE), improved ARM/Thumb switching, enhanced DSP instruction set (E), and Java acceleration (J).

1.2.6 ARM Version VI (V6)

Released in 2001 and first used in ARM11, V6 focused on lower power and better graphics. It introduced SIMD for multimedia, 35 % code compression (Thumb‑2), high‑performance DSP, Java acceleration (Jazelle, up to 8×), and media extensions (audio/video up to 4×).

2. ARM Product Models

2.1 Core Product Models

Core models derived from each architecture are shown in the diagram below:

ARMv7 and earlier are 32‑bit; ARMv8 expands to 64‑bit data, address, and control buses.

2.2 Product Naming Rules

ARM processor naming follows the pattern: ARM x y z T D M I E J F -S

x: series

y: 2 = with MMU, 4 = with MPU, 6 = none

z: 0 = standard cache, 2 = reduced cache, 6 = variable cache

T: supports Thumb instruction set

D: supports JTAG debugger

M: supports long‑multiply instruction

I: includes Embedded Trace Macrocell

E: supports enhanced instructions (based on TDMI)

J: supports Java acceleration (Jazelle)

F: includes floating‑point unit

S: synthesizable version

2.3 Core Product Applications

ARM7 – based on ARMv4, no MMU, used as MCU for RTOS such as uC/OS, uClinux.

ARM9 – based on ARMv5, includes MMU, can run Linux and other multi‑process OSes.

ARM11 – based on ARMv6, also includes MMU.

Cortex series – based on ARMv7, split into Cortex‑A (applications, virtual‑memory OS), Cortex‑R (real‑time), and Cortex‑M (microcontrollers).

In summary, the Cortex‑A series targets high‑performance mobile and application processors, while Cortex‑R and Cortex‑M are aimed at real‑time control and microcontroller markets respectively.

Source: compiled from various online resources by the Architecture Technologists Alliance.