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Cache Coherence

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Deepin Linux
Deepin Linux
Mar 27, 2025 · Fundamentals

Understanding Linux Memory Barriers: Concepts, Types, and Implementation

This article explains why modern multi‑core CPUs need memory barriers, describes the different kinds of barriers (full, read, write), shows how they are implemented in the Linux kernel and hardware, and illustrates their use in multithreaded and cache‑coherent programming.

CPU architectureCache CoherenceConcurrency
0 likes · 41 min read
Understanding Linux Memory Barriers: Concepts, Types, and Implementation
Deepin Linux
Deepin Linux
Feb 4, 2025 · Fundamentals

Understanding CPU Cache: Architecture, Hierarchy, and Optimization Techniques

This article explains the fundamental role of CPU cache in bridging the speed gap between processors and memory, covering cache hierarchy, locality principles, write policies, coherence protocols, and practical code optimizations such as data alignment and loop restructuring to improve performance.

CPU cacheCache CoherenceData Alignment
0 likes · 31 min read
Understanding CPU Cache: Architecture, Hierarchy, and Optimization Techniques
Tencent Cloud Developer
Tencent Cloud Developer
Nov 1, 2022 · Fundamentals

Understanding CPU Cache, Memory Hierarchy, and Virtual Memory

The article explains how modern computers use fast SRAM caches (L1‑L3) inside the CPU with various mapping schemes and the MESI coherence protocol to keep data consistent, while DRAM serves as main memory, and virtual memory with multi‑level page tables and a TLB abstracts physical memory, provides isolation, and enables swapping.

CPU cacheCache CoherenceMESI protocol
0 likes · 16 min read
Understanding CPU Cache, Memory Hierarchy, and Virtual Memory
Top Architect
Top Architect
Feb 1, 2022 · Fundamentals

Understanding CPU Cache Hierarchy, Cache Coherence, and Performance Optimization

This article explains the structure of modern CPU caches, the principles of cache lines, associativity, and coherence protocols, and demonstrates how these hardware details affect program performance through multiple code examples covering loop stride, matrix traversal, multithreading, and false sharing.

CPU cacheCache CoherencePerformance Optimization
0 likes · 21 min read
Understanding CPU Cache Hierarchy, Cache Coherence, and Performance Optimization
Liulishuo Tech Team
Liulishuo Tech Team
Mar 5, 2019 · Fundamentals

Understanding Concurrency: From Hardware Mechanisms to Language-Level Barriers

This article explains concurrency fundamentals by examining hardware-level cache coherence, memory barriers, and lock mechanisms, then shows how Go's sync.Mutex and Java's volatile keyword implement these concepts to ensure atomicity, visibility, and ordering across multiple cores.

Cache CoherenceConcurrencyGo
0 likes · 8 min read
Understanding Concurrency: From Hardware Mechanisms to Language-Level Barriers