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This article introduces the basic structure of a general‑purpose CPU used in AI chips, describing the arithmetic‑logic unit (ALU), the different types of registers, and the controller, while also directing readers to extensive AI‑chip technical report collections for deeper study.
The article analyses the historical evolution of Nvidia's NVLink and NVLink C2C interconnect technologies, compares them with PCIe, Ethernet and InfiniBand, and uses these trends to predict future AI‑chip architectures such as the B100 and X100 GPUs, highlighting design trade‑offs and packaging challenges.
Microsoft plans to announce its self‑developed AI processor, codenamed Athena, at the Ignite developer conference in mid‑November, aiming to reduce reliance on Nvidia GPUs and strengthen its AI services such as Azure AI, Bing Chat, and Copilot.
Microsoft plans to launch its first AI‑specific chip, codenamed Athena, at the upcoming Ignite conference, aiming to compete with Nvidia's H100 GPU, reduce reliance on Nvidia, and provide Azure and other cloud customers with a home‑grown AI accelerator for data‑center workloads.
This article provides a comprehensive technical review of Tesla's D1 AI processor and Dojo super‑computer architecture, covering its data‑flow near‑memory design, RISC‑V‑like instruction set, matrix compute units, chiplet packaging, power‑management, cooling solutions, and the associated software compilation ecosystem.
Kunlun Chip’s XPU‑R architecture combines high‑performance SDNN and Cluster compute units, 512 GB/s GDDR6 memory, and PCIe 4.0 interconnect, supported by an LLVM‑based software stack, CUDA‑like programming model, and seamless PaddlePaddle integration, enabling efficient AI training and inference with significant cost and performance gains.
The 2022 Beijing Zhiyuan Conference report by Kunlun Core’s chip R&D director outlines AI chip market opportunities and challenges, describes the company’s shift from FPGA clusters to a programmable XPU‑R architecture with 7nm, 256 TOPS INT8 performance, GDDR6 memory and PCIe 4.0, and details current deployments and plans for third‑ and fourth‑generation chips.
The article provides a comprehensive overview of AI chip technology, describing the dependence on mathematical models and semiconductor integration, classifying chips by architecture (GPU, FPGA, ASIC, SoC, brain‑like), deployment (cloud, edge, terminal), and outlining current challenges, market trends, and future research directions such as in‑memory and neuromorphic computing.
At the 2021 Tencent Digital Ecology Conference, senior executives unveiled three home‑grown chips—ZiXiao for AI inference, CangHai for video transcoding, and XuanLing for high‑performance networking—detailing their 2.5D HBM2e integration, accelerated codecs, and up to four‑fold performance improvements that position Tencent’s custom silicon as a core infrastructure for cloud services.
The article explains why dedicated AI chips (ASICs) are needed, compares their performance and power efficiency to traditional CPUs and GPUs, describes the architecture of Google's TPU and other AI accelerators, and provides historical context for the evolution of AI hardware.