Why China’s GPU Industry Can’t Leapfrog and How Domestic Makers Survive

In 2024 China’s GPGPU market reached 1.546 trillion CNY, with an expected near‑30% yearly growth that will push the market beyond 7 trillion CNY by 2029. The AI‑chip segment is forecast at 386 billion USD, with domestic share exceeding 60% and shipments surpassing 2.15 million units. Nvidia’s share has fallen to roughly 8%, while Huawei Ascend commands 44% and companies such as Wallin, Hai‑guang, Moore Thread and Mu‑xi each hold 8‑10%.

Policy pressure and export restrictions have forced a rapid shift: the United States blocks high‑end GPUs like A100 and H100, while Chinese data‑center mandates require >50% domestic chips, prompting a surge in demand that fuels domestic production.

Technically, 7 nm has become the baseline and chiplet packaging the breakthrough. Instead of pursuing ever‑smaller monolithic dies, Chinese vendors stack multiple 7 nm chiplets in 2.5 D packages, achieving PetaFLOPS‑level compute.

Key Domestic Players

Wallin Technology (壁仞科技) : BR100 (7 nm + chiplet) delivers 256 TFLOPS FP32—three times Nvidia’s A100—paired with 2 TB/s HBM2e bandwidth and can train 671 billion‑parameter models; over 1 billion USD in orders. The upgraded BR200 adds a self‑designed GPGPU architecture, >1 280 cores, 400 TFLOPS FP16 and near‑3 TB/s HBM3e bandwidth.

Moore Thread (摩尔线程) : MTT S5000 uses a 7 nm process, offers 1 000 TFLOPS FP8, 80 GB HBM with 1.6 TB/s bandwidth, and supports both gaming and AI workloads. Its self‑developed MUSA ISA eliminates foreign licensing, and the MUSIFY tool migrates CUDA code for a developer community exceeding 200 k.

Hai‑guang DCU (海光信息) : Focuses on x86‑compatible DCU cards, avoiding new ISA development. The 7 nm DCU series (models 8030/9040) feature chiplet packaging, cache‑bandwidth optimization and strong double‑precision performance, serving over 300 scenarios in finance, healthcare and other sectors.

Huawei Ascend (华为昇腾) : The 950 series, built on the Da Vinci V4 architecture, reaches 2.8 PFLOPS FP16 and 290 TFLOPS FP32, dominates edge‑inference with >45% market share, and integrates a full stack from silicon to AI frameworks.

Other notable products include Mu‑xi’s C600 (HBM3e, 1 000 TFLOPS FP8) for unified training‑inference and Jing‑jia‑wei’s JM9 series targeting industrial control and government‑grade reliability.

Despite rapid hardware advances, challenges remain. The software ecosystem trails Nvidia’s CUDA by 5‑10 years, with fewer than 4 000 developers, limited acceleration libraries, high migration costs and lower enterprise trust. Performance gaps of one to two generations persist for trillion‑parameter models, and supply‑chain dependencies on external IP and high‑end packaging strain profitability.

Overall, Chinese GPUs have moved beyond “can we build it?” to “how well can we compete?”. By leveraging 7 nm chiplets, 3D stacking, cache optimization and power‑efficiency, domestic vendors are carving differentiated paths in inference, edge, and government‑enterprise markets, turning policy‑driven demand into a sustainable growth engine.