Understanding DMA (Direct Memory Access) in STM32 Microcontrollers

DMA Definition

DMA (Direct Memory Access) provides high‑speed data transfer between peripherals and memory or between memory regions without CPU intervention, freeing the CPU for computation and control tasks.

DMA Transfer Modes

Four basic transfer directions are supported: peripheral‑to‑memory, memory‑to‑peripheral, memory‑to‑memory, and peripheral‑to‑peripheral. The controller moves data from a source address to a destination address based on configured parameters.

DMA Transfer Parameters

Key parameters include source address, destination address, transfer length, and transfer mode (including circular mode). The controller starts when these are set and stops when the remaining transfer count reaches zero.

Main Features

Four priority levels configurable via software.

Configurable data width (byte, half‑word, word) and address alignment.

Support for circular buffer management.

Three event flags per channel (half‑transfer, transfer‑complete, error) that can generate interrupts.

Supports transfers among flash, SRAM, APB1/2, AHB peripherals.

Maximum programmable transfer count 65535.

STM32 DMA Resources

High‑density STM32 parts provide two DMA controllers: DMA1 (7 channels) and DMA2 (5 channels), each mapped to specific peripherals such as TIM, ADC, SPI, I2C, USART, DAC, and SDIO.

DMA Operation Diagram

Illustrates how DMA, the core, memory, and peripherals are connected through the bus matrix, allowing independent data movement without CPU involvement.

Transfer without DMA vs with DMA

Without DMA the CPU must read data from a peripheral and write it to memory, consuming cycles. With DMA the peripheral requests the controller, which moves data directly to memory, eliminating CPU load.

DMA Transfer Process

Peripheral issues a request to DMA.

DMA acknowledges and starts the transfer.

Data is read from the peripheral and stored in the DMA channel.

DMA writes data to the destination memory via the bus matrix without CPU participation.

Arbitration

The arbiter resolves channel priority; software sets priority levels, and hardware resolves ties by channel number.

Memory‑to‑Memory Mode

Only DMA2 supports MEM2MEM transfers; the controller starts when the EN bit is set and runs until the transfer count reaches zero. This mode cannot be combined with circular mode.

Interrupts

Each channel can generate half‑transfer, transfer‑complete, and error interrupts. The DMA_ISR register holds status flags, while DMA_IFCR is used to clear them.

Register Configuration

Key registers include DMA_CCRx (control), DMA_CNDTRx (transfer count), DMA_CPARx (peripheral address), and DMA_CMARx (memory address). Proper configuration of these registers sets address, priority, direction, data width, increment mode, circular mode, and enables the channel.

Configuration Procedure

Set peripheral address in DMA_CPARx.

Set memory address in DMA_CMARx.

Set transfer count in DMA_CNDTRx.

Configure priority in DMA_CCRx PL bits.

Set direction, increment, data width, and interrupt enable in DMA_CCRx.

Enable the channel by setting the EN bit.