PCIe Device Enumeration and Memory Access Overview

PCIe, as the front‑end interface for NVMe SSDs, follows a hierarchical topology consisting of a root complex, switches, and endpoints, each identified by a Bus‑Device‑Function (BDF) address.

The host enumerates devices using a depth‑first algorithm, scanning each possible bus branch and configuring bridges by setting Primary, Secondary, and Subordinate Bus Number registers.

During enumeration, the host discovers bridges and endpoints across multiple buses (Bus 0 to Bus 5), assigning BDF identifiers and establishing the complete PCIe device topology.

In Linux, the lspci -v -t command displays the enumerated PCIe tree, and specific devices can be inspected with lspci -xxx -s 3C:00.0 or lspci -vvv -s 3C:00.0 , revealing configuration space details such as Vendor ID, Device ID, class code, and capability pointers.

Each PCIe device is allocated CPU memory address space; for example, the STAR1000 NVMe SSD provides two BARs of 1 MiB and 256 KiB, enabling the host to access device registers and memory‑mapped I/O.

NVMe command submission involves the host writing to a doorbell register (a memory‑write transaction) and the SSD issuing a memory‑read request to retrieve completion status, illustrating the bidirectional memory access model of PCIe.

The article concludes that understanding PCIe enumeration and memory access is essential for working with modern storage devices, and notes ongoing PCIe evolution toward higher‑speed generations such as Gen4 and Gen5.