Key Changes and Design Optimizations in PCIe 6.0 for High‑Performance SoC Development

PCI Express (PCIe) 6.0 implements a 64 GT/s link speed and introduces several major changes that affect SoC design, especially for HPC, AI, and storage applications.

Major new changes

Change 1: PAM‑4 signaling – To reach 64 GT/s, PCIe 6.0 uses 4‑level pulse‑amplitude modulation (PAM‑4), providing two bits per symbol. This increases BER, so the specification adds Gray coding, pre‑encoding, and forward error correction (FEC) to mitigate errors.

Change 2: FLIT mode – PCIe 6.0 introduces a fixed‑size Flow Control Unit (FLIT) packet format, simplifying controller data management, improving bandwidth efficiency, and reducing latency. At 64 GT/s the FLIT uses uncoded “1b1b” data, while lower speeds use 128/130 or 8b10b encoding.

Change 3: Wider PIPE data path – To keep the same clock frequency, the PIPE data path width doubles to 1024 bits (16 channels). This means a single clock cycle may need to handle multiple PCIe packets, increasing silicon area and logic complexity.

Optimization techniques

1. Relaxed ordering (RO) – Allows posted transactions to be delivered out of order when the RO attribute is set, improving throughput. Example tables illustrate how RO and ID ordering (IDO) affect multi‑interface performance.

2. Increasing application interfaces – Using multiple narrower interfaces can raise link utilization for small payloads. Figures show that a dual‑interface configuration achieves full utilization for 64‑byte payloads at 64 GT/s.

3. Addressing small‑packet inefficiency – Small posted packets suffer lower bandwidth. Simulation data from a 64 GT/s × 4 controller show how payload size and round‑trip time (RTT) affect efficiency.

Summary

SoC designers implementing 64 GT/s PCIe should enable relaxed ordering for payloads, support ID ordering where appropriate, consider multiple interfaces for small packets, and verify assumptions with pre‑silicon performance simulations. Vendors such as CoreConsultant provide complete PCIe 6.0 solutions (controller, PHY, VIP) that incorporate these optimizations.