Evolution and Applications of Network Cards: From Basic NICs to DPU SoC

Evolution and Application of Network Cards

With the development of cloud computing and virtualization, network adapters have gone through four stages: basic NICs, smart NICs, FPGA‑based DPUs, and DPU‑SoC cards. This article focuses on the characteristics of each type in terms of hardware, programmability, development, and application.

Basic NICs

Traditional NICs (also called network adapters) convert data into a format suitable for efficient transmission between network devices. Over time they have added hardware offload functions such as CRC checking, TSO/UFO, LSO/LRO, VLAN support, SR‑IOV for virtualization, and QoS for performance. Bandwidth has progressed from 100 M/1 G to 10 G, 25 G, and even 100 G.

In cloud‑virtualized networks, basic NICs provide three main ways to give virtual machines network access: (1) forwarding traffic through the OS kernel stack, (2) using DPDK user‑space drivers to bypass the kernel and copy packets directly to VM memory, and (3) employing SR‑IOV to virtualize the physical NIC into multiple virtual functions (VFs) assigned to VMs.

As tunnel protocols (e.g., VxLAN) and virtual switching increase network complexity, CPU demand rises. Smart NICs offload network processing from the CPU to improve overall performance.

Smart NICs

Smart NICs retain the basic data‑plane functions of NICs while adding hardware offload capabilities, often using FPGA or integrated processors for OVS/vRouter acceleration. They boost cloud network forwarding rates and reduce host CPU load.

Unlike traditional NICs, smart NICs do not contain a general‑purpose CPU; they rely on the host CPU for control‑plane management. Their offload focus is on the data plane, covering fast‑path virtual switches, RDMA, NVMe‑oF, and IPsec/TLS security offloads.

With ever‑increasing network speeds, cloud providers aim for “zero‑CPU consumption” by further offloading classification, tracking, and control tasks.

FPGA‑Based DPU

FPGA‑based DPUs are intelligent NICs that can offload data and provide partial programmability on both control and data planes. They typically combine an FPGA with a general‑purpose CPU (e.g., Intel CPU) to form an FPGA + CPU architecture, offering strong software and hardware programmability.

Compared with smart NICs, FPGA‑based DPUs integrate a CPU to enhance the hardware architecture, accelerating networking, storage, security, and management functions. Early DPU development offered short development cycles and rapid customization, but scaling from 25 G to 100 G bandwidth faces challenges due to chip process and FPGA limitations.

DPU‑SoC Cards

DPU‑SoC cards use ASIC‑based designs that combine dedicated accelerators with a general‑purpose processor, addressing cost, power, and functionality concerns for next‑generation 100 G servers. They support applications, VMs, containers, and bare‑metal workloads.

General‑purpose programmable DPU‑SoCs are now critical for cloud data‑center construction, efficiently managing compute and network resources across diverse cloud scenarios and improving resource utilization.

Amazon AWS Nitro DPU

AWS’s Nitro DPU system offloads networking, storage, security, and monitoring to dedicated hardware and software, allowing instances to access most server resources, reducing cost and increasing revenue. Nitro consists of Nitro cards, a Nitro security chip, and a lightweight Nitro hypervisor.

These components enable up to 100 Gbps network performance for certain instance types.

NVIDIA BlueField DPU

NVIDIA acquired Mellanox in 2020 and released the BlueField series. The BlueField‑3 DPU offers up to 400 G network connectivity and provides offload, acceleration, and isolation for software‑defined networking, storage, security, and management.

Intel IPU

Intel’s IPU is a network device equipped with hardened accelerators and Ethernet, using tightly coupled programmable cores to accelerate infrastructure functions. It offloads infrastructure workloads and serves as a secure control point, freeing server CPUs.

Intel’s roadmap includes FPGA‑based Oak Springs Canyon IPU (Agilex FPGA + Xeon‑D) and ASIC‑based Mount Evans IPU (ASIC + 16 ARM Neoverse N1 cores) co‑designed with Google.

Alibaba Cloud CIPU

Alibaba Cloud’s CIPU, based on the Shenlong architecture, continues the evolution of MoC cards through four generations, culminating in full hardware offload of network and storage operations with RDMA support.

Volcano Engine DPU

Volcano Engine develops its own DPU integrated with proprietary virtual switches and virtualization technology, delivering high‑performance cloud servers in its second‑generation elastic bare‑metal and third‑generation cloud instances.

These DPU solutions illustrate the industry’s shift toward programmable, high‑throughput, low‑CPU‑overhead networking in modern cloud infrastructures.