Code Migration Experience: Porting Business Applications from x86 to TaiShan aarch64 Servers

The author recounts the process of moving two projects' business code from x86 servers to TaiShan aarch64 servers, noting that the TaiShan platform runs the migrated code more efficiently.

Programming Language Overview

High‑level languages are divided into compiled (e.g., C, C++) and interpreted (e.g., Java, Python) categories. Compiled programs generate architecture‑specific machine code, so x86‑compiled binaries cannot run directly on TaiShan without recompilation. Interpreted programs produce platform‑independent bytecode, allowing them to run on TaiShan without changes, though native libraries (e.g., .so files) still need recompilation.

Preparation Work

For C/C++ migration, install GCC 7.3 or newer (minimum 4.8.5). Download links: http://ftp.gnu.org/gnu/gcc/gcc-7.3.0/ and installation guide https://gcc.gnu.org/install/ .

Compilation‑Related Issues

1.1 –m64 option : The x86‑specific -m64 flag is unsupported on ARM64; replace it with -mabi=lp64 .

1.2 char signedness : On x86, char defaults to signed; on ARM64 it defaults to unsigned. Add -fsigned-char to force signedness.

Source Code Modification Issues

2.1 Assembly rewrite : x86 assembly must be rewritten for ARM64, using GCC built‑ins where possible.

2.2 Replace x86 CRC32 instructions : Use ARM64 instructions crc32cb , crc32ch , crc32cw , crc32cx and add -mcpu=generic+crc to the compile flags.

2.3 Replace x86 bswap : Substitute bswap with ARM64 rev instruction.

2.4 Replace x86 rep : Replace the rep prefix with ARM64 rept .

2.5 Inline SSE/SSE2 : Use the open‑source https://github.com/open-estuary/sse2neon.git to provide ARM64 equivalents for SSE/SSE2 functions.

2.6 Weak memory ordering : ARM64’s weak memory model may cause out‑of‑order execution; use memory barrier instructions to ensure correctness, especially for lock‑free code.

2.7 Atomic operations on misaligned structs : Ensure struct members used in atomic operations are properly aligned; avoid #pragma pack that breaks alignment.

2.8 Hard‑coded core count : Search for hard‑coded CPU core numbers (e.g., in sched_setaffinity ) and replace them with dynamic queries like sysconf(_SC_NPROCESSORS_CONF) .

2.9 Double‑to‑integer conversion differences : ARM64 clamps overflow values to the target type’s limits, unlike x86’s “indefinite integer” behavior; adjust conversion logic accordingly.

Compiler Optimization Issues

4.1 GCC floating‑point contraction : The -ffp-contract=off flag disables fused multiply‑add (fmadd) to avoid precision differences between x86 and ARM64.

4.2 Architecture‑specific flags : Add -march=armv8-a to target Kunpeng processors.

4.3 Pipeline tuning : For GCC 9.1+, use -mtune=tsv110 to exploit Kunpeng’s pipeline.

Source: Huawei Developer Community.