2022 DPU Development Analysis Report and Related Network Technologies

On January 7, 2023, the China Academy of Information and Communications Technology together with the Open Data Center Committee released the "DPU Development Analysis Report (2022)". The report identifies DPU as the next‑generation chip technology, the third main chip in data centers after CPU and GPU.

DPU evolution has progressed from many‑core CPU‑NP and FPGA‑CPU architectures to ASIC‑CPU designs. Early CPU/NP and FPGA‑CPU solutions offered software and hardware programmability, which attracted large cloud vendors for rapid iteration and customization.

With network bandwidth rapidly increasing to 100 Gbps and 200 Gbps, CPU/NP and FPGA‑CPU architectures face performance limits, higher cost, and greater power consumption. ASIC‑CPU combines the flexibility of a general‑purpose CPU with dedicated acceleration engines, becoming the current product trend; leading vendors such as NVIDIA, Intel, and AMD (Pensando) adopt this architecture.

From a chip implementation perspective, ASIC‑CPU integrates third‑party multi‑core CPU IP, while competitive advantage lies in the custom acceleration engines. Because a DPU sits at the traffic ingress of all servers in a data center and processes packets, vendors with strong network‑chip expertise have a strategic edge.

RDMA High‑Speed Network Technology – Traditional TCP/IP processing involves multiple CPU context switches and memory copies, resulting in high latency. RDMA bypasses the OS and CPU by using DMA to move data directly between the memories of two hosts, providing CPU offload, kernel bypass, and zero‑copy capabilities.

Key RDMA benefits include:

CPU offload – applications can directly access remote memory via IB verbs without CPU involvement.

Kernel bypass – eliminates user‑kernel transitions and associated overhead.

Zero copy – data is transferred via NIC DMA without intermediate memory copies, reducing latency.

To achieve RDMA’s high performance, robust congestion control is required. Important factors are network convergence ratio, ECMP hash balancing, incast traffic patterns, and lossless switch flow‑control/QoS. Congestion control relies on ECN marking and CNP feedback to adjust sender rates.

Various congestion‑control algorithms (e.g., DCOCN, HPCC, TIMELY, Swift) have been validated in the field; therefore, DPU chips must support multiple algorithms or provide programmable congestion‑control capabilities.

RDMA’s application value lies in its higher throughput, lower CPU utilization, and reduced latency, especially when bandwidth exceeds 100 Gbps, making it a foundational transport for data‑center workloads.

Data‑Plane Forwarding Technologies – Two primary hardware forwarding architectures are discussed: the NP‑based Run‑to‑Completion (RTC) model and the pipeline model. RTC uses standard von Neumann cores programmed in C or microcode, while the pipeline splits processing into multiple stages, each handled by dedicated hardware units, achieving higher throughput and lower latency.

Comparing the two, pipeline architectures consume less silicon area, have lower power consumption, and deliver throughput and latency advantages over RTC, making programmable pipelines the preferred direction for DPU acceleration.

Network Programmable Technologies – DPU supports both control‑plane programmability (on general‑purpose SoCs) and data‑plane programmability (in hardware accelerators). Data‑plane programmability is realized via fast flow‑table mechanisms or P4 pipelines.

Open Network and DPU Software Ecosystem – The DPU software stack is still nascent. Major open initiatives include the Linux Foundation’s Open Programmable Infrastructure (OPI), Intel’s IPDK, NVIDIA’s DOCA, and the Open Data Center Committee’s lossless network project. Projects such as SONiC provide a vendor‑agnostic, open‑source platform that abstracts hardware differences through the SAI interface, enabling unified software across diverse devices.