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CPU cache

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Deepin Linux
Deepin Linux
Feb 4, 2025 · Fundamentals

Understanding CPU Cache: Architecture, Hierarchy, and Optimization Techniques

This article explains the fundamental role of CPU cache in bridging the speed gap between processors and memory, covering cache hierarchy, locality principles, write policies, coherence protocols, and practical code optimizations such as data alignment and loop restructuring to improve performance.

CPU cacheCache CoherenceData Alignment
0 likes · 31 min read
Understanding CPU Cache: Architecture, Hierarchy, and Optimization Techniques
Deepin Linux
Deepin Linux
Sep 26, 2024 · Fundamentals

Understanding CPU Cache Hierarchy, Write‑Back Strategy, and Memory Ordering in Multithreaded Programming

This article explains the structure and operation of modern CPU multi‑level caches, the write‑back caching policy, cache‑coherence mechanisms, atomic operations, and various memory‑ordering models in C++ multithreaded programs, providing detailed concepts, hardware and software solutions, and practical code examples.

CCPU cacheMultithreading
0 likes · 32 min read
Understanding CPU Cache Hierarchy, Write‑Back Strategy, and Memory Ordering in Multithreaded Programming
Tencent Cloud Developer
Tencent Cloud Developer
Apr 25, 2024 · Fundamentals

Cache, Prefetching, False Sharing, Pipeline and Data Dependency: Performance Optimization in Rust

The article uses Rust benchmarks to show how cache layout, prefetching, associativity, false sharing, pipeline stalls, and loop data dependencies impact performance, and demonstrates practical optimizations such as row‑major traversal, proper alignment, avoiding dependent loops, and leveraging sequential access to achieve near‑optimal speed.

CPU cachePipelineRust
0 likes · 17 min read
Cache, Prefetching, False Sharing, Pipeline and Data Dependency: Performance Optimization in Rust
Tencent Technical Engineering
Tencent Technical Engineering
Apr 2, 2024 · Fundamentals

Cache, Prefetching, False Sharing, Pipeline, and Data Dependency: Benchmarks and Optimizations in Rust

The article shows how row‑major vs column‑major traversal, random access, cache‑set conflicts, false sharing, branch‑prediction failures, and loop‑carried data dependencies each degrade performance by tying Rust (and C++) code patterns to CPU cache behavior, prefetching, pipeline stalls, and vectorization limits, demonstrated through runnable benchmarks.

CPU cachePipelineRust
0 likes · 15 min read
Cache, Prefetching, False Sharing, Pipeline, and Data Dependency: Benchmarks and Optimizations in Rust
New Oriental Technology
New Oriental Technology
May 25, 2023 · Fundamentals

Deep Dive into Java volatile: CPU Cache Architecture, MESI Protocol, JMM and Happens‑Before

This article thoroughly explains the low‑level implementation of Java's volatile keyword by analysing CPU multi‑level cache design, the MESI cache‑coherency protocol, the Java Memory Model, memory barriers, the happens‑before principle, and the impact on singleton patterns and synchronized blocks.

CPU cacheHappens-BeforeJMM
0 likes · 36 min read
Deep Dive into Java volatile: CPU Cache Architecture, MESI Protocol, JMM and Happens‑Before
Tencent Cloud Developer
Tencent Cloud Developer
Nov 1, 2022 · Fundamentals

Understanding CPU Cache, Memory Hierarchy, and Virtual Memory

The article explains how modern computers use fast SRAM caches (L1‑L3) inside the CPU with various mapping schemes and the MESI coherence protocol to keep data consistent, while DRAM serves as main memory, and virtual memory with multi‑level page tables and a TLB abstracts physical memory, provides isolation, and enables swapping.

CPU cacheCache CoherenceMESI protocol
0 likes · 16 min read
Understanding CPU Cache, Memory Hierarchy, and Virtual Memory
Selected Java Interview Questions
Selected Java Interview Questions
Jul 27, 2022 · Fundamentals

Understanding Java's volatile Keyword: CPU Cache, Memory Visibility, and the MESI Protocol

This article explains how the volatile keyword ensures visibility in Java multithreaded programs by examining CPU cache architecture, cache‑coherency mechanisms such as the MESI protocol, and the low‑level assembly effects of volatile writes on modern x86 processors.

CPU cacheJavaMESI
0 likes · 12 min read
Understanding Java's volatile Keyword: CPU Cache, Memory Visibility, and the MESI Protocol
Top Architect
Top Architect
Feb 1, 2022 · Fundamentals

Understanding CPU Cache Hierarchy, Cache Coherence, and Performance Optimization

This article explains the structure of modern CPU caches, the principles of cache lines, associativity, and coherence protocols, and demonstrates how these hardware details affect program performance through multiple code examples covering loop stride, matrix traversal, multithreading, and false sharing.

CPU cacheCache CoherenceMultithreading
0 likes · 21 min read
Understanding CPU Cache Hierarchy, Cache Coherence, and Performance Optimization
Ops Development Stories
Ops Development Stories
Jul 15, 2021 · Operations

Mastering NUMA and Hyper-Threading: Boost CPU Cache Hits and Reduce Latency

This article explains NUMA architecture with hyper‑threading, details CPU cache hierarchies and access latencies, and provides Linux tools and practical optimization techniques to improve cache‑hit rates and minimize cross‑NUMA memory delays.

CPU cacheNUMAPerformance Tuning
0 likes · 9 min read
Mastering NUMA and Hyper-Threading: Boost CPU Cache Hits and Reduce Latency
vivo Internet Technology
vivo Internet Technology
Jan 6, 2021 · Fundamentals

Deep Dive into Java Volatile Keyword: CPU Cache, MESI Protocol, and JMM

The article thoroughly explains how CPU caches and the MESI coherence protocol interact with Java’s Memory Model, detailing the volatile keyword’s role in ensuring visibility and preventing instruction reordering, and illustrates these concepts with examples such as visibility problems and double‑checked locking.

CPU cacheJMMJava
0 likes · 22 min read
Deep Dive into Java Volatile Keyword: CPU Cache, MESI Protocol, and JMM
Xiaokun's Architecture Exploration Notes
Xiaokun's Architecture Exploration Notes
Jan 30, 2020 · Fundamentals

How False Sharing Slows Java Programs and How to Eliminate It

This article explains the concept of false sharing in CPU caches, demonstrates its performance impact with Java code, analyzes the results, and shows how to prevent it using the @Contended annotation and appropriate JVM flags.

CPU cacheContended annotationJava performance
0 likes · 9 min read
How False Sharing Slows Java Programs and How to Eliminate It
Beike Product & Technology
Beike Product & Technology
Nov 2, 2018 · Fundamentals

Physical Memory Model, Concurrency Concepts, and Java Memory Model Explained

This article explains the modern computer physical memory hierarchy, introduces three key concurrency concepts—atomicity, ordering, and visibility—illustrates them with Java code examples, and then details the Java Memory Model and its eight happen‑before principles that govern multithreaded behavior.

CPU cacheHappen-BeforeMemory Model
0 likes · 14 min read
Physical Memory Model, Concurrency Concepts, and Java Memory Model Explained
Qunar Tech Salon
Qunar Tech Salon
Oct 31, 2018 · Backend Development

Understanding Cache: Concepts, Types, and Performance Optimization in High-Concurrency Scenarios

This article explains cache fundamentals—from CPU and local caches to distributed systems—covers design principles, performance‑affecting factors, eviction algorithms, and common high‑concurrency issues such as penetration, stampede, and avalanche, and provides practical solutions for selecting and optimizing cache strategies.

CPU cacheCache EvictionPerformance Optimization
0 likes · 16 min read
Understanding Cache: Concepts, Types, and Performance Optimization in High-Concurrency Scenarios
Architecture Digest
Architecture Digest
May 5, 2017 · Fundamentals

Understanding False Sharing: CPU Cache, MESI Protocol, and Java Mitigation Techniques

This article explains the concept of false sharing, its roots in CPU cache line contention and the MESI protocol, demonstrates its impact with Java benchmark code, and presents practical padding and alignment techniques to mitigate the performance degradation caused by false sharing.

CPU cacheJava ConcurrencyMESI protocol
0 likes · 15 min read
Understanding False Sharing: CPU Cache, MESI Protocol, and Java Mitigation Techniques
Qunar Tech Salon
Qunar Tech Salon
Mar 31, 2015 · Fundamentals

Understanding CPU Caches, Coherency Protocols, and Memory Models

This article provides a concise introduction to CPU cache architecture, explains read/write policies, describes cache coherency protocols such as MESI and its variants, and discusses how different memory models affect multi‑core consistency and performance.

CPU cacheCache CoherencyHardware Architecture
0 likes · 19 min read
Understanding CPU Caches, Coherency Protocols, and Memory Models
Qunar Tech Salon
Qunar Tech Salon
Mar 23, 2015 · Fundamentals

Understanding CPU Cache: Purpose, Multi‑Level Design, Cache Lines, and Optimization Techniques

This article explains why CPU caches are needed, the evolution to multi‑level caches, the concept of cache lines, practical experiments demonstrating their impact, and how different cache organization strategies such as fully associative, direct‑mapped, and N‑way set‑associative affect performance and eviction policies.

CPU cachePerformance Optimizationcache architecture
0 likes · 14 min read
Understanding CPU Cache: Purpose, Multi‑Level Design, Cache Lines, and Optimization Techniques