Understanding Ethernet: MAC, PHY, MII, and SMI Interfaces

Ethernet is a widely used LAN technology that transfers data between computers and network devices using a shared‑medium protocol with CSMA/CD for collision detection.

Originally developed by Xerox, Intel, and DEC, Ethernet now offers high‑speed, reliable, and cost‑effective connections, with standards like 10BASE‑T, 100BASE‑TX, and 1000BASE‑T defining different data rates and media types.

1. Introduction

The network interface card (NIC) operates at the physical and data‑link layers of the OSI model. The physical layer defines electrical/optical signals, line states, clocking, encoding, and provides a standard interface to the data‑link layer; its chip is called a PHY.

The OSI model, defined by ISO in 1985, consists of seven layers: Physical, Data Link, Network, Transport, Session, Presentation, and Application.

The NIC’s data‑link layer provides addressing, frame construction, error checking, flow control, and an interface to the network layer. The MAC controller handles these functions, often combined with the PHY on the same chip. The PCI bus connects to the MAC, which connects to the PHY, which then connects to the Ethernet cable (with a transformer in between).

The MII/GigaMII (Media Independent Interface) links MAC and PHY, while the MAC controls the PHY via the Serial Management Interface (SMI) by reading and writing PHY registers.

SMI uses two lines, MDC (clock) and MDIO (bidirectional data), similar to I²C, allowing a MAC to access up to 32 PHY devices.

2. System Overview

From a hardware perspective, an Ethernet interface typically consists of a CPU, a MAC controller, and a PHY. These components may be integrated in various ways: CPU‑integrated MAC with separate PHY, CPU‑integrated MAC and PHY, or completely separate chips.

The MII interface provides three functions: data transmission from MAC to PHY, data reception from PHY to MAC, and register control via MDIO.

SMI is a two‑wire serial interface (MDC and MDIO) used by the MAC to poll PHY status and issue commands.

3. Communication Methods

MII (Media Independent Interface) is the IEEE‑802.3 standard that connects MAC and PHY. Variants include MII, RMII, GMII, SGMII, RGMII, etc. MII uses 16 signals and a 25 MHz clock to support 10/100 Mbps, full‑/half‑duplex, and 4‑bit data paths.

RMII simplifies MII by halving the data lines, using a 50 MHz clock, and is common in multi‑port switches.

For gigabit Ethernet, GMII and its reduced‑pin version RGMII are used; RGMII samples data on both clock edges to achieve 125 MHz effective bandwidth.

4. MAC

The Media Access Control (MAC) sublayer resides in the lower half of the OSI data‑link layer and controls the interface to the physical medium, handling frame construction, transmission control, and error checking.

When transmitting, the MAC adds control information and sends the frame to the PHY. When receiving, it checks for errors, strips control data, and passes the payload to the Logical Link Control (LLC) layer.

5. PHY

The PHY implements the OSI physical layer, converting parallel digital data from the MAC into serialized analog signals for transmission, and vice‑versa for reception.

PHY registers are defined in a 5‑bit address space (32 registers). Registers 0‑15 are standardized across all PHYs, while 16‑31 are vendor‑specific. Linux provides a generic PHY driver that works with any compliant PHY, though vendor‑specific features may require custom drivers.

6. Conclusion

The MAC is a digital controller operating at the data‑link layer, while the PHY is an analog transceiver at the physical layer. Integration of MAC and PHY on a single chip is challenging because the PHY contains extensive analog circuitry, but advances in mixed‑signal processes are making such integration increasingly feasible.