Understanding Data Storage: RAM, DRAM, and Memory Controllers
This article explains how digital data is stored using memory modules, describing the principles of static SRAM, dynamic DRAM, the role of capacitors and refresh cycles, and how memory controllers manage addressing and integrate with CPUs and caches.
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1. How to Store Data
Because data storage is crucial, scientists have long considered how to preserve data in circuits.
If a device continuously outputs a high level, that represents a 1; a low level represents a 0, and it must be switchable between the two.
Enter the memory module.
2. RAM
Memory modules are formally called RAM (Random Access Memory) because they allow arbitrary read/write of any location.
Computers use binary representation, so all data and instructions are sequences of bits (0s and 1s).
Two circuit approaches have been used to store a single bit. The first is a static solution.
This static scheme, called SRAM (Static Random Access Memory), can reliably hold a state between 0 and 1.
However, SRAM requires many transistors per bit, making large capacities expensive and physically large.
The second approach uses a single capacitor to store a bit: the charge on the capacitor determines whether the bit is 1 or 0.
In a 16 GB memory module, there are 137 438 953 472 such capacitors, each representing one bit.
Capacitors leak charge over time, causing the voltage to decay and making it impossible to distinguish 1 from 0.
To solve this, the cells must be periodically refreshed, a technique known as dynamic refresh, giving rise to DRAM (Dynamic Random Access Memory).
3. Memory Controller
When reading data, the system must specify the chip, bank, row address, and column address to locate a particular bit.
These details are encapsulated by a memory controller, which provides a simple interface.
The memory controller sits between the CPU and the memory modules.
Because capacitors leak, the controller must refresh each cell at least every 64 ms.
Data is stored across many chips, each divided into banks and rows/columns; the controller translates a linear address into these coordinates.
Modern CPUs integrate the memory controller, and because CPUs are faster than memory, they also include caches to store frequently accessed data.
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