Analysis of Armv9 Microarchitectures: A710, A715, and A510

This article reviews the Armv9 processor family, focusing on the big cores A710 and A715 and the little core A510. It begins with a brief recap of the previous Armv8 era and introduces the new Armv9 architecture released in March 2021, highlighting its improvements in performance, security, and AI capabilities.

Cortex‑X Custom CPU Plan : Before Armv9, Arm launched the Cortex‑X series (e.g., Cortex‑X1) as a “super‑big” core. The plan allows OEMs to customize the core design, offering larger chip area, more issue slots, larger caches, and a claimed >30% performance gain over the A78.

64‑bit Application Ecosystem : Apple required 64‑bit apps in iOS 11 (2017) and Google required 64‑bit Android apps in 2021. Armv9’s first‑generation A510 and Cortex‑X2 do not support 32‑bit code, while A710 does. Subsequent revisions (A510r, A715) added or removed 32‑bit support, influencing power consumption and performance when running legacy apps.

SVE2 Extension : Armv9 introduces Scalable Vector Extension 2 (SVE2), extending the previous NEON/SVE vector units. SVE2 vectors can scale from 128 bits up to 2048 bits, enabling higher‑throughput SIMD operations for AI and multimedia workloads.

Product Code Names : A710 = Matterhorn, A715 = Makalu, A510 = Klein, with next‑generation codenames Hunter (A715) and Hayes (A510).

A710 Microarchitecture : The first Armv9 big core, supporting both 32‑bit and 64‑bit code and introducing SVE2. Compared to A78, A710 keeps a similar front‑end but doubles branch‑predictor capacity and L1 TLB size. It reduces dispatch width from 6 to 5, saves area, and improves energy efficiency (≈10% performance gain at equal power, ≈30% power reduction at equal performance in high‑frequency region). Real‑world power/efficiency improvements were observed after moving from Samsung to TSMC process in Snapdragon 8 Gen 1 → 8 + Gen 1.

A715 Microarchitecture : A pure‑64‑bit core that removes 32‑bit support and the MOP cache, adds an extra decode lane (5‑wide decode), and uses smaller distributed decoders. Branch predictor capacity is doubled, supporting two branch predictions per cycle, and instruction‑cache bandwidth is also doubled. Energy‑efficiency gains are modest (≈5% performance increase, ≈20% power reduction at equal performance). The core is used in Snapdragon 8 Gen 2 and MediaTek Dimensity 9200.

A510 Microarchitecture : The Armv9 little core, successor to the A55. It remains in‑order (no OoO), but widens pipelines (fetch, decode, issue from 2‑wide to 3‑wide) and doubles ALU count. It shares a VPU (handling scalar FP, NEON, SVE2) between two cores and uses a tiled‑core layout with shared L2 cache and TLB. Performance improves ≈35% over A55, with ≈20% energy‑efficiency gain in high‑frequency regions. A510r adds back 32‑bit support.

Overall Summary : Armv9’s A710, A715, and A510 illustrate a gradual evolution rather than a radical redesign. The big cores focus on branch‑predictor and dispatch optimizations, while the little core gains width and shared resources. Energy‑efficiency improvements are evident but limited by the continued use of in‑order execution for A510. The article also notes industry trends such as shifting from the traditional 1+3+4 core configuration to alternatives like 1+4+3 in Snapdragon 8 Gen 2.